Add support for mediatek's SDG1 NFC nand controller embedded in SoC
2701
Signed-off-by: NJorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
Tested-by: NXiaolei Li <xiaolei.li@mediatek.com>

In case of error, the function dmaengine_prep_slave_sg() returns NULL
pointer not ERR_PTR(). The IS_ERR() test in the return value check
should be replaced with NULL test.
Signed-off-by: NWei Yongjun <yongjun_wei@trendmicro.com.cn>
Fixes: 614049a8 ("mtd: nand: sunxi: add support for DMA assisted operations")
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

This change provides a fix for controller bug where nand
controller could have a possible sticky error after a PIO
followed by a DMA read. The fix retries a read if we see
a uncorr_ecc after read to detect such sticky errors.
The fix applies to only controller version 7.0 and 7.1.
Signed-off-by: NKamal Dasu <kdasu.kdev@gmail.com>
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

Check for erased page bitflips in a page. And if well within
threshold return data as all 0xff. Apply sw check for controller
version < 7.2. Controller vesion >= 7.2 has hw support.
Signed-off-by: NKamal Dasu <kdasu.kdev@gmail.com>
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

I got device with ESMT (Elite Semiconductor Memory Technology Inc)
F59L1G81MA flash that was detected as:
[    0.852034] nand: device found, Manufacturer ID: 0xc8, Chip ID: 0xd1
[    0.858402] nand: Unknown NAND 128MiB 3,3V 8-bit
[    0.863031] nand: 128MiB, SLC, page size: 2048, OOB size: 64

According to the F59L1G81MA datasheet (and Read Id documentation) C8h is
a "Maker Code" which should mean ESMT. Add it to fix above "Unknown".
Signed-off-by: NRafał Miłecki <zajec5@gmail.com>
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

The sunxi NAND controller is able to pipeline ECC operations only when
operated in DMA mode, which improves a lot NAND throughput while keeping
CPU usage low.
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

The 7.2 controller differs in a few area compared to its predecssor (7.1):

- NAND scrambler, which we are not using just yet
- higher ECC levels (up to 120 bits) per 1KB data blocks, also not supported yet
- up to 128B OOB

This patch adds the necessary code to support such a controller
generation and updates the Device Tree binding.
Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com>
Acked-by: NKamal Dasu <kdasu.kdev@gmail.com>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

Switch from dma_request_channel to allow passing dma channel
information from DT rather than hardcoding a value.

Also provide a handle to the GPMC's dev so it can be used to parse the DMA
channel information within the GPMC's DT node.

Performance Numbers via mtd_speedtest now that EDMA based prefetch works:

AM335x Performance numbers:
DMA
  CPULOAD Write: 54%  Read: 35%
  page write speed	-23% (vs non dma)
  page read speed	-35% (vs non dma)

NO DMA (prefetch-polled)
  CPULOAD Write: 98%  Read: 98%

AM437x Performance numbers:
DMA
  CPU LOAD Write: 56% Read: 36%
  page write speed	-16% (vs non dma)
  page read speed	-22% (vs non dma)

NO DMA (prefetch-polled)
  CPULOAD Write: 93%  Read: 93%
Signed-off-by: NFranklin S Cooper Jr <fcooper@ti.com>
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

This reverts commit 5ddc7bd4 ("mtd: atmel_nand: Support variable
RB_EDGE interrupts")

Because for current SoCs, the RB_EDGE3(i.e. bit 27) of HSMC_SR
register does not exist, the RB_EDGE0 (i.e. bit 24) is the ready/busy
line edge status bit. It is a datasheet bug.

Cc: <stable@vger.kernel.org>
Fixes: commit 5ddc7bd4 ("mtd: atmel_nand: Support variable RB_EDGE interrupts")
Signed-off-by: NWenyou Yang <wenyou.yang@atmel.com>
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>

Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
Acked-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

This is more obvious than guessing based on ECC strength. It allows
using NAND on devices with BCH-1 (e.g. D-Link DIR-885L).

This maintains DT backward compatibility by defaulting to Hamming if a
1-bit ECC algorithm is specified without a corresponding algorithm
selection. i.e., to use BCH-1, you must specify:

  nand-ecc-strength = <1>;
  nand-ecc-step-size = <512>;
  nand-ecc-algo = "bch";

Also adds a check to ensure we haven't allowed someone to get by with SW
ECC. If we want to support SW ECC, we need to refactor some other pieces
of this driver.
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
Tested-by: NRafał Miłecki <zajec5@gmail.com>
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

ECC is only calculated for written pages. As erased pages are not
actively written the ECC is always invalid. For this purpose the
Hardware BCH unit is able to check for erased pages and does not raise
an ECC error in this case. This behaviour can be influenced using the
BCH_MODE register which sets the number of allowed bitflips in an erased
page. Unfortunately the unit is not capable of fixing the bitflips in
memory.

To avoid complete software checks for erased pages, we can simply check
buffers with uncorrectable ECC errors because we know that any erased
page with errors is uncorrectable by the BCH unit.

This patch adds the generic nand_check_erased_ecc_chunk() to gpmi-nand
to correct erased pages. To have the valid data in the buffer before
using them, this patch moves the read_page_swap_end() call before the
ECC status checking for-loop.
Signed-off-by: NMarkus Pargmann <mpa@pengutronix.de>
[Squashed patches by Stefan and Boris to check ECC area]
Tested-by: NStefan Christ <s.christ@phytec.de>
Acked-by: NHan xu <han.xu@nxp.com>
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

So far it was only possible to specify ECC algorithm using "soft" and
"soft_bch" values of nand-ecc-mode prop. There wasn't a way to specify
it for a hardware ECC mode.

Now that we have independent field in NAND subsystem for storing info
about ECC algorithm we may also add support for this new DT property.
Signed-off-by: NRafał Miłecki <zajec5@gmail.com>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

This value should not be part of nand_ecc_modes_t as it specifies
algorithm not a mode. We successfully managed to introduce new "algo"
field which is respected now.
Signed-off-by: NRafał Miłecki <zajec5@gmail.com>
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

There isn't any difference between handling NAND_ECC_SOFT and
NAND_ECC_SOFT_BCH now. What matters is the new field called "algo".
Please note we're keeping backward DT compatibility. We are still
treating "soft_bch" value as the one setting Hamming algorithm, it's
just handled in of_get_nand_ecc_algo now.
Signed-off-by: NRafał Miłecki <zajec5@gmail.com>
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

Now we have all drivers properly setting this new field we can start
using it. For a very short period of time we should support both values:
NAND_ECC_SOFT and NAND_ECC_SOFT_BCH treating them the same. It's because
of_get_nand_ecc_mode may still be setting NAND_ECC_SOFT_BCH.
Signed-off-by: NRafał Miłecki <zajec5@gmail.com>
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

NAND core sets ECC algorithm in algo field now and it should be
preferred over the mode field. This also prepares driver for dropping
NAND_ECC_SOFT_BCH.
Signed-off-by: NRafał Miłecki <zajec5@gmail.com>
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

This is part of process deprecating NAND_ECC_SOFT_BCH (and switching to
enum nand_ecc_algo).
Signed-off-by: NRafał Miłecki <zajec5@gmail.com>
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

This is part of process deprecating NAND_ECC_SOFT_BCH (and switching to
enum nand_ecc_algo).
Signed-off-by: NRafał Miłecki <zajec5@gmail.com>
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

This is part of process deprecating NAND_ECC_SOFT_BCH (and switching to
enum nand_ecc_algo).
Signed-off-by: NRafał Miłecki <zajec5@gmail.com>
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

This is part of process deprecating NAND_ECC_SOFT_BCH (and switching to
enum nand_ecc_algo).
Signed-off-by: NRafał Miłecki <zajec5@gmail.com>
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

Based on DMA documentation and testing using high memory buffer when doing
dma transfers can lead to various issues including kernel panics.

To workaround this simply use cpu copy.
Signed-off-by: NFranklin S Cooper Jr <fcooper@ti.com>
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

The prefetch engine sends a dma request once a FIFO threshold has
been met. No other requests are received until the previous request
is handled.

Starting a dma transfer (dma_async_issue_pending) results in any
previous event for the dma channel to be cleared. Therefore, starting
the prefetch engine before initiating the dma transfer may result in
the prefetch triggering a dma request but instead of it being handled
it can end up being cleared. This will result in a hang since the code
will continue to wait for the dma request to complete.

By initiating the dma request before enabling the prefetch engine this
race condition is avoided and no dma request are missed/cleared.
Signed-off-by: NFranklin S Cooper Jr <fcooper@ti.com>
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

Add __init attribute on functions that are only called from other __init
functions and that are not inlined, at least with gcc version 4.8.4 on an
x86 machine with allyesconfig.  Currently, the functions are put in the
.text.unlikely segment.  Declaring them as __init will cause them to be
put in the .init.text and to disappear after initialization.

The result of objdump -x on the functions before the change is as follows:

000000000000059a l     F .text.unlikely 0000000000000239 alloc_device
000000000000034e l     F .text.unlikely 000000000000002e get_partition_name
00000000000007d3 l     F .text.unlikely 00000000000005da init_nandsim

And after the change it is as follows:

0000000000000029 l     F .init.text	0000000000000234 alloc_device
0000000000000000 l     F .init.text	0000000000000029 get_partition_name
000000000000025d l     F .init.text	00000000000005d5 init_nandsim

Done with the help of Coccinelle.  The semantic patch checks for local
static non-init functions that are called from an __init function and are
not called from any other function.
Signed-off-by: NJulia Lawall <Julia.Lawall@lip6.fr>
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

Now that all drivers go through nand_set_flash_node() to parse the generic
NAND properties, we can move all of_get_nand_xxx() helpers in to
nand_base.c, make them static and remove of_mtd.c and of_mtd.h.
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

The core now takes care of parsing generic DT properties in
nand_scan_ident() when nand_set_flash_node() has been called.
Rely on this initialization instead of calling of_get_nand_xxx()
manually.
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

The core now takes care of parsing generic DT properties in
nand_scan_ident() when nand_set_flash_node() has been called.
Rely on this initialization instead of calling of_get_nand_xxx()
manually.
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

The core now takes care of parsing generic DT properties in
nand_scan_ident() when nand_set_flash_node() has been called.
Rely on this initialization instead of calling of_get_nand_xxx()
manually.
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

The core now takes care of parsing generic DT properties in
nand_scan_ident() when nand_set_flash_node() has been called.
Rely on this initialization instead of calling of_get_nand_xxx()
manually.
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

The core now takes care of parsing generic DT properties in
nand_scan_ident() when nand_set_flash_node() has been called.
Rely on this initialization instead of calling of_get_nand_xxx()
manually.
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

The core now takes care of parsing generic DT properties in
nand_scan_ident() when nand_set_flash_node() has been called.
Rely on this initialization instead of calling of_get_nand_xxx()
manually.
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: NHan xu <han.xu@nxp.com>

Move constants to the right of binary operators.

Generated by: scripts/coccinelle/misc/compare_const_fl.cocci

CC: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: NFengguang Wu <fengguang.wu@intel.com>
Signed-off-by: NJulia Lawall <julia.lawall@lip6.fr>
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

Signed-off-by: NMaarten ter Huurne <maarten@treewalker.org>
Acked-by: NHarvey Hunt <harvey.hunt@imgtec.com>
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

This is part of process deprecating NAND_ECC_SOFT_BCH (and switching to
enum nand_ecc_algo).
Signed-off-by: NRafał Miłecki <zajec5@gmail.com>
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

This is part of process deprecating NAND_ECC_SOFT_BCH (and switching to
enum nand_ecc_algo).
Signed-off-by: NRafał Miłecki <zajec5@gmail.com>
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

This is part of process deprecating NAND_ECC_SOFT_BCH (and switching to
enum nand_ecc_algo).
Signed-off-by: NRafał Miłecki <zajec5@gmail.com>
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

This is part of process deprecating NAND_ECC_SOFT_BCH (and switching to
enum nand_ecc_algo).
Signed-off-by: NRafał Miłecki <zajec5@gmail.com>
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

This is part of process deprecating NAND_ECC_SOFT_BCH (and switching to
enum nand_ecc_algo).
Signed-off-by: NRafał Miłecki <zajec5@gmail.com>
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

This is part of process deprecating NAND_ECC_SOFT_BCH (and switching to
enum nand_ecc_algo).
Signed-off-by: NRafał Miłecki <zajec5@gmail.com>
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

This is part of process deprecating NAND_ECC_SOFT_BCH (and switching to
enum nand_ecc_algo).
Signed-off-by: NRafał Miłecki <zajec5@gmail.com>
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>