1. 27 1月, 2008 18 次提交
  2. 26 1月, 2008 10 次提交
  3. 11 1月, 2008 1 次提交
  4. 24 12月, 2007 2 次提交
  5. 13 12月, 2007 2 次提交
    • S
      hpt366: fix HPT37x PIO mode timings (take 2) · 809b53c4
      Sergei Shtylyov 提交于
      After looking into the HPT370 manual (now that I have it) and re-checking all
      the timing tables, here's what I have discovered:
      
      - at 33 MHz clock, PIO mode 0 timings turned to be overclocked, and all other
        PIO modes underclocked;
      
      - at 50 MHz clock, PIO modes 0 to 2 turned to be overclocked;
      
      - at 66 MHz clock, PIO mode 0 was overclocked too.
      
      Finally, the taskfile timing (matching PIO mode 0) turned to be overclocked at
      all clock frequencies (and in all manuals)...
      
      The new timings have been tested on HPT370 chip (at 33 MHz PCI clock) and on
      HPT371N chip (at both 50 and 66 MHz DPLL clock).
      Signed-off-by: NSergei Shtylyov <sshtylyov@ru.mvista.com>
      Signed-off-by: NBartlomiej Zolnierkiewicz <bzolnier@gmail.com>
      809b53c4
    • B
      pdc202xx_new: fix Promise TX4 support · eadb6ecf
      Bartlomiej Zolnierkiewicz 提交于
      In case of Promise TX4 the first PCI device is located at slot 1
      and the second one is at slot 2 so the offset used by pci_get_slot()
      should be "+1" and not "+2".
      
      Thanks goes out to Markus Dietz for bugreport and testing this patch.
      
      Cc: Sergei Shtylyov <sshtylyov@ru.mvista.com>
      Signed-off-by: NBartlomiej Zolnierkiewicz <bzolnier@gmail.com>
      eadb6ecf
  6. 28 11月, 2007 6 次提交
  7. 14 11月, 2007 1 次提交