The mach/io.h header on at91 is used to support a nonstandard I/O space
window for the cf card driver. This changes the driver to use pci_ioremap_io
in order to have the standard location, and then removes the custom
mach/io.h.

[alexandre.belloni@free-electrons.com: Added PCI dependency]
Signed-off-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

Flush data cache, and clean, invalidate and disable the L2 cache before going to suspend.
Restore the L2 cache configuration and re-enable the L2 cache after waking up.
Signed-off-by: NWenyou Yang <wenyou.yang@atmel.com>
Acked-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>
Tested-by: NSylvain Rochet <sylvain.rochet@finsecur.com>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

Add the WFI instruction to make the cpu to the idle state.
In the meanwhile, disable the processor's clock.
Signed-off-by: NWenyou Yang <wenyou.yang@atmel.com>
Acked-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>
Tested-by: NSylvain Rochet <sylvain.rochet@finsecur.com>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

Because the standby mode use the same sram function as the suspend to memory
mode, void (*at91_pm_standby)(void) doesn't need, remove it.
Signed-off-by: NWenyou Yang <wenyou.yang@atmel.com>
Tested-by: NSylvain Rochet <sylvain.rochet@finsecur.com>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

As the file name is renamed, rename the function name at91_slow_clock()
--> at91_pm_suspend_sram_fn(), rename the function handler's name at the
same time.
Signed-off-by: NWenyou Yang <wenyou.yang@atmel.com>
Acked-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>
Tested-by: NSylvain Rochet <sylvain.rochet@finsecur.com>
[nicolas.ferre@atmel.com: little update of the commit message]
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

Because the sram function is used for both suspend to memory and the suspend
to standby mode, renaming is more elegant.
Signed-off-by: NWenyou Yang <wenyou.yang@atmel.com>
Acked-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>
Tested-by: NSylvain Rochet <sylvain.rochet@finsecur.com>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

To simply the PM code, the suspend to standby mode uses same sram function
as the suspend to memory mode, running in the internal SRAM, instead of the
respective code for each mode.

For the suspend to standby mode, the master clock doesn't switch to the slow
clock, and PLLA and the main oscillator doesn't turn off as well.
Signed-off-by: NWenyou Yang <wenyou.yang@atmel.com>
Tested-by: NSylvain Rochet <sylvain.rochet@finsecur.com>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

To decrease the suspend time, move copying the sram function to the sram
initialization phase, instead of every time go to suspend.

In the meanwhile, substitute fncpy() for memcpy().

If there is no sram allocated for PM, the PM is not supported.
Signed-off-by: NWenyou Yang <wenyou.yang@atmel.com>
Acked-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>
Tested-by: NSylvain Rochet <sylvain.rochet@finsecur.com>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

To decrease the duplicated code, create the procedure
to contain both activing and exiting the sdram self-refresh mode.
Signed-off-by: NWenyou Yang <wenyou.yang@atmel.com>
Tested-by: NSylvain Rochet <sylvain.rochet@finsecur.com>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

Assume USB PLL and PLL B are already stopped before entering sleep mode.

Removed PLL B from slow clock code, all drivers are supposed to properly
unprepare clocks.
Signed-off-by: NSylvain Rochet <sylvain.rochet@finsecur.com>
Acked-by: NWenyou.Yang <wenyou.yang@atmel.com>
[nicolas.ferre@atmel.com: remove the warning printed in pm.c]
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

The slow clock always exists, selecting CONFIG_AT91_SLOW_CLOCK config
is unnecessary for the suspend to memory mode.
For this mode the master clock should always switch to the slow clock.
Signed-off-by: NWenyou Yang <wenyou.yang@atmel.com>
Acked-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>
Tested-by: NSylvain Rochet <sylvain.rochet@finsecur.com>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

To simply the PM config the CONFIG_AT91_SLOW_CLOCK option will be removed,
so move "select SRAM" from under AT91_SLOW_CLOCK, add "select SRAM if PM"
under SOC_AT91SAM9 and SOC_SAMA5
Signed-off-by: NWenyou Yang <wenyou.yang@atmel.com>
Acked-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>
Tested-by: NSylvain Rochet <sylvain.rochet@finsecur.com>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

The SLOWDOWN_MASTER_CLOCK definition is not used, remove the redundant code.
Signed-off-by: NWenyou Yang <wenyou.yang@atmel.com>
Acked-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>
Tested-by: NSylvain Rochet <sylvain.rochet@finsecur.com>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

Since at91_pm_set_standby() will not be used out of the pm.c file,
change its attribute from extern to static, remove its declaration as well.
Signed-off-by: NWenyou Yang <wenyou.yang@atmel.com>
Acked-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

Commit 2b0ba96c ("net: phy: micrel: disable NAND-tree for KSZ8021,
KSZ8031, KSZ8051, KSZ8081") automated the NAND-tree mode deactivation
process, thus making this phy fixup useless.
Remove it along with the associated headers inclusion.
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>
[nicolas.ferre@atmel.com: remove selection of PHYLIB in at91 Kconfig]
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

Third fixes batch for AT91 on 4.0:
- clock fixes for USB
- compatible string changes for handling USB IP differences
  (+ needed AHB matrix syscon)
- fix of a compilation error in PM code

Second fixes batch for AT91 on 4.0:
- little fix for !MMU debug: may also help for randconfig
- fix of 2 errors in LCD clock definitions
- in PM code, not writing the key leads to not execute the action

First fixes batch for AT91 on 4.0:
- PM slowclock fixes for DDR and timeouts
- fix some DT entries
- little defconfig updates
- the removal of a harmful watchdog option + its detailed documentation

When compiling the kernel in thumb2 (CONFIG_THUMB2_KERNEL option activated), we
hit a compilation crash. The error message is listed below:

---8< -----
Error: cannot use register index with PC-relative addressing -- `str r0,.saved_lpr'
--->8----

Add the .arm directive in the assembly files related to power management.
Signed-off-by: NWenyou Yang <wenyou.yang@atmel.com>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

The UTMI clock must be selected by any high-speed USB IP. The logic behind it
needs this particular clock.
So, correct the clock in the device tree files affected.
Reported-by: NBo Shen <voice.shen@atmel.com>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>
Cc: <stable@vger.kernel.org> #3.18

The at91rm9200, at91sam9260, at91sam9261 and at91sam9263 SoCs have slightly
different UDC IPs.
Those differences were previously handled with cpu_is_at91xx macro which
are about to be dropped for multi-platform support, thus we need to
change compatible strings.
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

There is no specific driver handling the AHB matrix, this is a simple syscon
device. the matrix is needed by several other drivers including the USB on some
SoCs (at91sam9261 for instance).
Without this definition, the USB will not work on these SoCs.
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

Peripheral clock is named pclk and system clock is named hclk (those are
the names expected by the at91_udc driver).

Drop the deprecated usb_clk (formerly used to configure the usb clock rate
which is now directly configurable through hclk).
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

Because writing the MOR register requires the PASSWD(0x37),
if missed, the write operation will be aborted.
Signed-off-by: NPatrice Vilchez <patrice.vilchez@atmel.com>
Acked-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

lcdck takes mck (not smd) as its parent. It is also assigned id 3 and not 4.
Signed-off-by: NBoris BREZILLON <boris.brezillon@free-electrons.com>
[nicolas.ferre@atmel.com: squashed 2 related patches]
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

Rename lcd_clk into lcdc_clk to be consistent with sama5d3 clock
definitions.
Signed-off-by: NBoris BREZILLON <boris.brezillon@free-electrons.com>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

Linux may be used without MMU on atmel SoCs, fix debug in this configuration.
Signed-off-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

Since turning on idle-halt in commit fe46aa67 (ARM: at91/dt: add
sam9 watchdog default options to SoCs), SoCs compatible with at91sam9260-wdt
no longer reboot if the watchdog times out while the CPU is in idle state.
Removing the 'idle-halt' flag that was set by default fixes this.
Signed-off-by: NMichel Marti <mma@objectxp.com>
Acked-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: NSylvain Rochet <sylvain.rochet@finsecur.com>
[nicolas.ferre@atmel.com: rework the commit message]
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

atmel,idle-halt property should be used with care, it actually makes the
watchdog not counting when the CPU is in idle state, therefore the
watchdog reset time depends on mean CPU usage and will not reset at all
of the CPU stop working while it is in idle state, which is probably not
what you want.
Signed-off-by: NSylvain Rochet <sylvain.rochet@finsecur.com>
Acked-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

There is now only one defconfig for the at91rm9200 and at91sam9. Add ethernet
support for the at91rm9200.
Signed-off-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

Recent distributions and userspace tools after 2009/2010 depend on
the existence of /sys/class/block/, and will not work with this option enabled.
Signed-off-by: NAnthony Harivel <anthony.harivel@emtrion.de>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

Corrected pins used by usart3.
Signed-off-by: NJonas Andersson <jonas@microbit.se>
Acked-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

Commit ff04660e48b20 ("ARM: at91/dt: add SRAM nodes") used the same base
address for sram0 and sram1 leading to the following warning:
WARNING: CPU: 0 PID: 1 at fs/sysfs/dir.c:31 sysfs_warn_dup+0x50/0x70()
sysfs: cannot create duplicate filename '/devices/platform/300000.sram'
Fix the base address for sram1.
Signed-off-by: NAlexander Stein <alexanders83@web.de>
Acked-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

On some platforms, there are multiple SRAM nodes defined in the device tree but
some of them are disabled, leading to allocation failure. Try to find the first
enabled SRAM node and allocate from it.
Signed-off-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>
Tested-by: NWenyou Yang <wenyou.yang@atmel.com>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

at91rm9200 standby and suspend to ram has been broken since
00482a40. It is wrongly using AT91_BASE_SYS which is a physical address
and actually doesn't correspond to any register on at91rm9200.

Use the correct at91_ramc_base[0] instead.

Fixes: 00482a40 (ARM: at91: implement the standby function for pm/cpuidle)
Signed-off-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

The DDRSDR controller fails miserably to put LPDDR1 memories in
self-refresh. Force the controller to think it has DDR2 memories
during the self-refresh period, as the DDR2 self-refresh spec is
equivalent to LPDDR1, and is correctly implemented in the
controller.

Assume that the second controller has the same fault, but that is
untested.
Signed-off-by: NPeter Rosin <peda@axentia.se>
Acked-by: NNicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

Removed timeout on XTAL, PLL lock and Master Clock Ready, hang if
something went wrong instead of continuing in unknown condition. There
is not much we can do if a PLL lock never ends, we are running in SRAM
and we will not be able to connect back the sdram or ddram in order to
be able to fire up a message or just panic.

As a bonus, not decounting the timeout register in slow clock mode
reduce cumulated suspend time and resume time from ~17ms to ~15ms.
Signed-off-by: NSylvain Rochet <sylvain.rochet@finsecur.com>
Acked-by: NWenyou.Yang <wenyou.yang@atmel.com>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

This is a tricky story of the new atomic state handling and the legacy
code fighting over each another. The bug at hand is an underrun of the
framebuffer reference with subsequent hilarity caused by the load
detect code. Which is peculiar since the the exact same code works
fine as the implementation of the legacy setcrtc ioctl.

Let's look at the ingredients:

- Currently our code is a crazy mix of legacy modeset interfaces to
  set the parameters and half-baked atomic state tracking underneath.
  While this transition is going we're using the transitional plane
  helpers to update the atomic side (drm_plane_helper_disable/update
  and friends), i.e. plane->state->fb. Since the state structure owns
  the fb those functions take care of that themselves.

  The legacy state (specifically crtc->primary->fb) is still managed
  by the old code (and mostly by the drm core), with the fb reference
  counting done by callers (core drm for the ioctl or the i915 load
  detect code). The relevant commit is

  commit ea2c67bb
  Author: Matt Roper <matthew.d.roper@intel.com>
  Date:   Tue Dec 23 10:41:52 2014 -0800

      drm/i915: Move to atomic plane helpers (v9)

- drm_plane_helper_disable has special code to handle multiple calls
  in a row - it checks plane->crtc == NULL and bails out. This is to
  match the proper atomic implementation which needs the crtc to get
  at the implied locking context atomic updates always need. See

  commit acf24a39
  Author: Daniel Vetter <daniel.vetter@ffwll.ch>
  Date:   Tue Jul 29 15:33:05 2014 +0200

      drm/plane-helper: transitional atomic plane helpers

- The universal plane code split out the implicit primary plane from
  the CRTC into it's own full-blown drm_plane object. As part of that
  the setcrtc ioctl (which updated both the crtc mode and primary
  plane) learned to set crtc->primary->crtc on modeset to make sure
  the plane->crtc assignments statate up to date in

  commit e13161af
  Author: Matt Roper <matthew.d.roper@intel.com>
  Date:   Tue Apr 1 15:22:38 2014 -0700

      drm: Add drm_crtc_init_with_planes() (v2)

  Unfortunately we've forgotten to update the load detect code. Which
  wasn't a problem since the load detect modeset is temporary and
  always undone before we drop the locks.

- Finally there is a organically grown history (i.e. don't ask) around
  who sets the legacy plane->fb for the various driver entry points.
  Originally updating that was the drivers duty, but for almost all
  places we've moved that (plus updating the refcounts) into the core.
  Again the exception is the load detect code.

Taking all together the following happens:
- The load detect code doesn't set crtc->primary->crtc. This is only
  really an issue on crtcs never before used or when userspace
  explicitly disabled the primary plane.

- The plane helper glue code short-circuits because of that and leaves
  a non-NULL fb behind in plane->state->fb and plane->fb. The state
  fb isn't a real problem (it's properly refcounted on its own), it's
  just the canary.

- Load detect code drops the reference for that fb, but doesn't set
  plane->fb = NULL. This is ok since it's still living in that old
  world where drivers had to clear the pointer but the core/callers
  handled the refcounting.

- On the next modeset the drm core notices plane->fb and takes care of
  refcounting it properly by doing another unref. This drops the
  refcount to zero, leaving state->plane now pointing at freed memory.

- intel_plane_duplicate_state still assume it owns a reference to that
  very state->fb and bad things start to happen.

Fix this all by applying the same duct-tape as for the legacy setcrtc
ioctl code and set crtc->primary->crtc properly.

Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Paul Bolle <pebolle@tiscali.nl>
Cc: Rob Clark <robdclark@gmail.com>
Cc: Paulo Zanoni <przanoni@gmail.com>
Cc: Sean Paul <seanpaul@chromium.org>
Cc: Matt Roper <matthew.d.roper@intel.com>
Reported-and-tested-by: NLinus Torvalds <torvalds@linux-foundation.org>
Reported-by: NPaul Bolle <pebolle@tiscali.nl>
Signed-off-by: NDaniel Vetter <daniel.vetter@intel.com>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>