This commit implements the ARM timer-based delay timer for the
LPC32xx, LPC18xx, LPC43xx family of SoCs.

Also, add a dependency to restrict compiling this driver for
the ARM architecture.
Signed-off-by: NEzequiel Garcia <ezequiel@vanguardiasur.com.ar>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>
Reviewed-by: NJoachim Eastwood <manabian@gmail.com>
Tested-by: NJoachim Eastwood <manabian@gmail.com>

This commit adds the support for periodic mode. This is done by not
setting the MR0S (Stop on TnMR0) bit on MCR, thus allowing
interrupts to be periodically generated on MR0 matches.

In order to do this, move the initial configuration that is specific to
the one-shot mode to set_state_oneshot().
Signed-off-by: NEzequiel Garcia <ezequiel@vanguardiasur.com.ar>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>
Reviewed-by: NJoachim Eastwood <manabian@gmail.com>
Tested-by: NJoachim Eastwood <manabian@gmail.com>

This commit switches the clockevents one-shot current implementation
to avoid using the prescaler counter. The clockevents timer currently
uses MR0=1, PR=ticks; and after this commit is uses MR0=ticks, PR=0.

While using the prescaler with PR=1 works fine in one-shot mode,
it seems it doesn't work as expected in periodic mode.

By using the only match channel register (MR0) for the timer we make
the periodic mode introduction easier, and consistent with one-shot mode.
Signed-off-by: NEzequiel Garcia <ezequiel@vanguardiasur.com.ar>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>
Reviewed-by: NJoachim Eastwood <manabian@gmail.com>
Tested-by: NJoachim Eastwood <manabian@gmail.com>

Currently rockchip_timer doesn't do some basic cleanup work when
failing to init the timer. Let's add err handle routine to deal
with all the err cases.
Signed-off-by: NShawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>

So far, we have been blindly assuming that having access to a
memory-mapped timer frame implies that the individual elements of that
frame frame are already enabled. Whilst it's the firmware's job to give
us non-secure access to frames in the first place, we should not rely
on implementations always being generous enough to also configure CNTACR
for those non-secure frames (e.g. [1]).

Explicitly enable feature-level access per-frame, and verify that the
access we want is really implemented before trying to make use of it.

[1]:https://github.com/ARM-software/tf-issues/issues/170Acked-by: NMark Rutland <mark.rutland@arm.com>
Reviewed-by: NStephen Boyd <sboyd@codeaurora.org>
Tested-by: NStephen Boyd <sboyd@codeaurora.org>
Acked-by: NMarc Zyngier <marc.zyngier@arm.com>
Signed-off-by: NRobin Murphy <robin.murphy@arm.com>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>

The vt8500 clocksource driver declares itself as capable to handle the
minimum delay of 4 cycles by passing the value into
clockevents_config_and_register(). The vt8500_timer_set_next_event()
requires the passed cycles value to be at least 16. The impact is that
userspace hangs in nanosleep() calls with small delay intervals.

This problem is reproducible in Linux 4.2 starting from:
c6eb3f70 ('hrtimer: Get rid of hrtimer softirq')

From Russell King, more detailed explanation:

"It's a speciality of the StrongARM/PXA hardware. It takes a certain
number of OSCR cycles for the value written to hit the compare registers.
So, if a very small delta is written (eg, the compare register is written
with a value of OSCR + 1), the OSCR will have incremented past this value
before it hits the underlying hardware. The result is, that you end up
waiting a very long time for the OSCR to wrap before the event fires.

So, we introduce a check in set_next_event() to detect this and return
-ETIME if the calculated delta is too small, which causes the generic
clockevents code to retry after adding the min_delta specified in
clockevents_config_and_register() to the current time value.

min_delta must be sufficient that we don't re-trip the -ETIME check - if
we do, we will return -ETIME, forward the next event time, try to set it,
return -ETIME again, and basically lock the system up. So, min_delta
must be larger than the check inside set_next_event(). A factor of two
was chosen to ensure that this situation would never occur.

The PXA code worked on PXA systems for years, and I'd suggest no one
changes this mechanism without access to a wide range of PXA systems,
otherwise they're risking breakage."

Cc: stable@vger.kernel.org
Cc: Russell King <linux@arm.linux.org.uk>
Acked-by: NAlexey Charkov <alchark@gmail.com>
Signed-off-by: NRoman Volkov <rvolkov@v1ros.org>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>

Select CLKSRC_MMIO when FSL_FTM_TIMER is enabled. Otherwise it fails to
compile on i386 with COMPILE_TEST=y.

"
on i386:
when CLKSRC_MMIO is not enabled:

drivers/built-in.o: In function `ftm_timer_init':
fsl_ftm_timer.c:(.init.text+0x6842): undefined reference to `clocksource_mmio_readl_up'
fsl_ftm_timer.c:(.init.text+0x6855): undefined reference to `clocksource_mmio_init'
"
Reported-by: NRandy Dunlap <rdunlap@infradead.org>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>

Not every arch has io memory.

So, unbreak the build by fixing the dependencies.
Signed-off-by: NRichard Weinberger <richard@nod.at>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>

Like it's already done in one place in the driver, convert the rest to use pr_*
macros instead of printk(KERN_LEVEL) calls.

While here, join strings to be one string for one line to make grep on them
easier.

There is no functional change.
Signed-off-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Link: http://lkml.kernel.org/r/1451310085-113182-1-git-send-email-andriy.shevchenko@linux.intel.comSigned-off-by: NThomas Gleixner <tglx@linutronix.de>

Signed-off-by: NYoshinori Sato <ysato@users.sourceforge.jp>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>

Signed-off-by: NYoshinori Sato <ysato@users.sourceforge.jp>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>

Signed-off-by: NYoshinori Sato <ysato@users.sourceforge.jp>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>

Signed-off-by: NYoshinori Sato <ysato@users.sourceforge.jp>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>

Counter overflow detection use for overflow interrupt
Signed-off-by: NYoshinori Sato <ysato@users.sourceforge.jp>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>

If by some reason timerclk is not available, both clockevent and
clocksource initializations correctly exit, but output of errno to
kernel log buffer may be confusing:

  lpc32xx_clk_init: failed to map system control block registers
  lpc32xx_clocksource_init: clock get failed (4294966779)
  lpc32xx_clockevent_init: clock get failed (4294966779)

Use signed integer output in the correspondent pr_err() string formats:

  lpc32xx_clocksource_init: clock get failed (-517)
  lpc32xx_clockevent_init: clock get failed (-517)
Signed-off-by: NVladimir Zapolskiy <vz@mleia.com>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>

Now the System stall is observed on TI AM437x based board (am437x-gp-evm)
during resuming from System suspend when ARM Global timer is selected as
clocksource device (CPUIdle not enabled) - SysRq are working, but nothing
else.

The reason of stall is that ARM Global timer loses its contexts during
System suspend:
   GT_CONTROL.TIMER_ENABLE = 0 (unbanked)
   GT_COUNTERx = 0

Hence, update ARM Global timer driver to reflect above behaviour
- re-enable ARM Global timer on resume (GT_CONTROL.TIMER_ENABLE = 1)
  if not enabled.

CC: Arnd Bergmann <arnd@arndb.de>
Cc: John Stultz <john.stultz@linaro.org>
Cc: Felipe Balbi <balbi@ti.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Reviewed-by: NSantosh Shilimkar <ssantosh@kernel.org>
Signed-off-by: NGrygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>

Let's assume the counter value is 0xf0000000, the pistachio clocksource
read cycles function should return ~0x0fffffff but actually it returns
0xffffffff0fffffff.

That occurs because:

	~(cycle_t)value is different from (cycle_t)~value.

unsigned long val = ~(unsigned long)0xf0000000;
40049a:       48 b8 ff ff ff 0f ff    movabs $0xffffffff0fffffff,%rax

unsigned long val = (unsigned long)~0xf0000000;
40049a:       48 c7 45 f8 ff ff ff    movq   $0xfffffff,-0x8(%rbp)

We fix this issue by calculating bitwise-not counter, then cast to
cycle_t.
Signed-off-by: NJisheng Zhang <jszhang@marvell.com>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>

Use the relaxed version to improve performance. we measured time of
4096 rounds of gt_compare_set() spent on Marvell BG2Q:

before the patch: 3690648ns on average
after the patch: 1083023ns on average

improved by 70%!
Signed-off-by: NJisheng Zhang <jszhang@marvell.com>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>

It seems gcc can automatically inline apbt_writel() for us, but
apbt_real isn't inlined. This patch makes them inline to get a trivial
performance improvement: 4096 rounds of __apbt_read_clocksource() call
spend time on Marvell BG4CT platform:

 before the patch 1275240ns on average
 after the patch 1263240ns on average

so we get 1% performance improvement.
Signed-off-by: NJisheng Zhang <jszhang@marvell.com>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>

It's safe to use the relaxed version. From another side, the relaxed io
accessor macros are available on all architectures now, so we can use
the relaxed versions to get a trivial system performance improvement,
we measured time the following functions spent on Marvell BG4CT:

4096 rounds of __apbt_read_clocksource() call:

before the patch: 1263240ns on average
after the patch: 1250080ns on average
improved by 1%

4096 rounds of apbt_eoi() call:

before the patch: 1290960ns on average
after the patch: 1248240ns on average

4096 rounds of apbt_next_event() call:

before the patch: 3333660ns on average
after the patch: 1322040ns on average

improved by 60%!
Signed-off-by: NJisheng Zhang <jszhang@marvell.com>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>

On Marvell BG4CT platform, we observed the __apbt_read_clocksource()
return wrong value: Let's assume the APBTMR_N_CURRENT_VALUE value is
0xf0000000, we got 0xffffffff0fffffff, but it should be 0xfffffff.

This issue should be common on all 64bit platforms. We fix the issue
by letting aptb_readl() return u32. apbt_writel() is also updated
to write u32 val rather than unsigned long.
Signed-off-by: NJisheng Zhang <jszhang@marvell.com>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>

The current code to initialize, register and read the clocksource is
already factored out in mmio.c via the clocksource_mmio_init function.

Factor out the code with the clocksource_mmio_init function.
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>

Add the COMPILE_TEST option so the drivers can be compiled on different
architecture with the 'allyesconfig' kernel configuration.
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>

For the sake of consistency, let rename all ctrl_out/in calls to the write/read
calls so we have the same API consistent with the other architectures hence
open the door for the increasing of the test compilation coverage.

The unsigned long coercive cast is removed because all variables are set to
the right type "void __iomem *".
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>

The current Kconfig option is the H8300 arch option. In order to comply to the
current rule, let's create a specific option for the timer8 and select it
from the arch's Kconfig.
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>

The current code to initialize, register and read the clocksource is
already factored out in mmio.c via the clocksource_mmio_init function.

The only difference is the readl vs readl_relaxed.

Factor out the code with the clocksource_mmio_init function.
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>
Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

The lock in the timer16_clocksource_read is not needed, remove it.
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>

The function irq_of_parse_and_map returns zero in case of failure.

Fix the return code test to check against zero.
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>

The fields are not used in the code, remove them.
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>

The macros are no longer used in the code, remove them.
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>

The headers are not needed, remove them.
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>

The current code retrieves the rate value when the timer is enabled which
occurs each time a timer is re-armed. Except if the clock frequency has changed
magically I don't see why this should be done each time.

Retrieve the clock rate value at init time only.
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>

The time framawork takes care of disabling the interrupts and takes a lock
to prevent races.

Remove the legacy code in the driver taking care of the races.
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>

The current code assumes the interrupt function is re-entrant.

That is not correct. An interrupt handler is never invoked concurrently. The
interrupt line is masked on all processors.

Remove the chewing flags in the code.
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>

The value returned in case of error for the 'irq_of_parse_and_map' function is
zero in case of error. Fix the check in the init code.
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>

Specify the delta as parameter for the timer8_clock_event_start function
instead of using a macro to tell PERIODIC or ONESHOT.
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>

Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>

Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>

Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>

Some macros are unused, delete them.
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>