1. 27 6月, 2017 1 次提交
  2. 14 6月, 2017 3 次提交
  3. 12 6月, 2017 2 次提交
  4. 07 4月, 2017 3 次提交
    • L
      clocksource/drivers/gemini: Rename Gemini timer to Faraday · f5bf0ee4
      Linus Walleij 提交于
      After some research it turns out that the "Gemini" timer is
      actually a generic IP block from Faraday Technology named
      FTTMR010, so as to not make things too confusing we need to
      rename the driver and its symbols to make sense.
      
      The implementation remains the same in this patch but we fix
      the copy-paste error in the timer name "nomadik_mtu" as we're
      at it.
      Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
      Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>
      f5bf0ee4
    • A
      clocksource/drivers/rockchip_timer: Implement clocksource timer · 5e0a39d0
      Alexander Kochetkov 提交于
      The clock supplying the arm-global-timer on the rk3188 is coming from the
      the cpu clock itself and thus changes its rate everytime cpufreq adjusts
      the cpu frequency making this timer unsuitable as a stable clocksource
      and sched clock.
      
      The rk3188, rk3288 and following socs share a separate timer block already
      handled by the rockchip-timer driver. Therefore adapt this driver to also
      be able to act as clocksource and sched clock on rk3188.
      
      In order to test clocksource you can run following commands and check
      how much time it take in real. On rk3188 it take about ~45 seconds.
      
          cpufreq-set -f 1.6GHZ
          date; sleep 60; date
      
      In order to use the patch you need to declare two timers in the dts
      file. The first timer will be initialized as clockevent provider
      and the second one as clocksource. The clockevent must be from
      alive subsystem as it used as backup for the local timers at sleep
      time.
      
      The patch does not break compatibility with older device tree files.
      The older device tree files contain only one timer. The timer
      will be initialized as clockevent, as expected.
      
      rk3288 (and probably anything newer) is irrelevant to this patch,
      as it has the arch timer interface. This patch may be useful
      for Cortex-A9/A5 based parts.
      Signed-off-by: NAlexander Kochetkov <al.kochet@gmail.com>
      Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>
      5e0a39d0
    • M
      arm64: arch_timer: Workaround for Cortex-A73 erratum 858921 · fa8d815f
      Marc Zyngier 提交于
      Cortex-A73 (all versions) counter read can return a wrong value
      when the counter crosses a 32bit boundary.
      
      The workaround involves performing the read twice, and to return
      one or the other depending on whether a transition has taken place.
      Acked-by: NThomas Gleixner <tglx@linutronix.de>
      Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>
      fa8d815f
  5. 08 2月, 2017 5 次提交
    • D
      clocksource/drivers/arm_arch_timer: Work around Hisilicon erratum 161010101 · bb42ca47
      Ding Tianhong 提交于
      Erratum Hisilicon-161010101 says that the ARM generic timer counter "has
      the potential to contain an erroneous value when the timer value
      changes". Accesses to TVAL (both read and write) are also affected due
      to the implicit counter read. Accesses to CVAL are not affected.
      
      The workaround is to reread the system count registers until the value
      of the second read is larger than the first one by less than 32, the
      system counter can be guaranteed not to return wrong value twice by
      back-to-back read and the error value is always larger than the correct
      one by 32. Writes to TVAL are replaced with an equivalent write to CVAL.
      Signed-off-by: NDing Tianhong <dingtianhong@huawei.com>
      [Mark: split patch, fix Kconfig, reword commit message]
      Signed-off-by: NMark Rutland <mark.rutland@arm.com>
      Acked-by: NDaniel Lezcano <daniel.lezcano@linaro.org>
      Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>
      bb42ca47
    • D
      clocksource/drivers/arm_arch_timer: Introduce generic errata handling infrastructure · 16d10ef2
      Ding Tianhong 提交于
      Currently we have code inline in the arch timer probe path to cater for
      Freescale erratum A-008585, complete with ifdeffery. This is a little
      ugly, and will get worse as we try to add more errata handling.
      
      This patch refactors the handling of Freescale erratum A-008585. Now the
      erratum is described in a generic arch_timer_erratum_workaround
      structure, and the probe path can iterate over these to detect errata
      and enable workarounds.
      
      This will simplify the addition and maintenance of code handling
      Hisilicon erratum 161010101.
      Signed-off-by: NDing Tianhong <dingtianhong@huawei.com>
      [Mark: split patch, correct Kconfig, reword commit message]
      Signed-off-by: NMark Rutland <mark.rutland@arm.com>
      Acked-by: NDaniel Lezcano <daniel.lezcano@linaro.org>
      Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>
      16d10ef2
    • C
      clocksource/drivers/ostm: Add renesas-ostm timer driver · fb6002a8
      Chris Brandt 提交于
      This patch adds a OSTM driver for the Renesas architecture.
      The OS Timer (OSTM) has independent channels that can be
      used as a freerun or interval times.
      This driver uses the first probed device as a clocksource
      and then any additional devices as clock events.
      Signed-off-by: NChris Brandt <chris.brandt@renesas.com>
      Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>
      fb6002a8
    • L
      clocksource/drivers/gemini: Add driver for the Cortina Gemini · 4750535b
      Linus Walleij 提交于
      This is a rewrite of the Gemini timer
      driver in arch/arm/mach-gemini/timer.c trying to do everything
      the device tree way:
      
      - Make every IO-access relative to a base address and dynamic
        so we can do a dynamic ioremap and get going.
      - Do not poke around directly in the global syscon registers,
        access them using the syscon regmap style design pattern for
        the one register we need to check.
      - Find register range and interrupt from the device tree.
      
      Cc: Janos Laube <janos.dev@gmail.com>
      Cc: Paulius Zaleckas <paulius.zaleckas@gmail.com>
      Cc: Hans Ulli Kroll <ulli.kroll@googlemail.com>
      Cc: Florian Fainelli <f.fainelli@gmail.com>
      Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
      Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>
      4750535b
    • D
      clockevents: Add a clkevt-of mechanism like clksrc-of · 376bc271
      Daniel Lezcano 提交于
      The current code uses the CLOCKSOURCE_OF_DECLARE macro to fill the clksrc
      table with a t-uple (name, init_function).
      
      Unfortunately it ends up to the clockevent and the clocksource being
      both initialized with this macro. It is not a problem by itself but there
      is not a clear distinction between a clockevent and a clocksource in the
      code initialization path. Somebody can argue there are the same IP block
      and the same DT node. But conceptually from the software side, there are
      two distincts entities and as is they should be initialized separetely.
      Some drivers which do not have a clocksource end up by using the
      CLOCKSOURCE_OF_DECLARE macro to declare a clockevent.
      
      Another result is the fuzzy organization in the clocksource directory,
      where the clockevents are implemented in the same file than the
      clocksources or file labelled timer-something implementing a clocksource.
      
      This patch provides another macro to specifically declare a clockevent in
      the same way than the clocksource and gives the opportunity to write two
      separate drivers, one for the clocksource and another for the clockevents.
      
      Hopefully, that can help to do some housework in the directory, perhaps
      split the drivers in to entities, for example:
      	- clksrc-rockchip.c
      	- clkevt-rockchip.c
      
      Also, it gives the possibility to declare clocksources separately in the
      DT and then use a clocksource from IP block while while clockevents are
      used from another IP block.
      Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>
      376bc271
  6. 01 12月, 2016 1 次提交
  7. 21 10月, 2016 1 次提交
    • R
      clocksource: Add J-Core timer/clocksource driver · 9995f4f1
      Rich Felker 提交于
      At the hardware level, the J-Core PIT is integrated with the interrupt
      controller, but it is represented as its own device and has an
      independent programming interface. It provides a 12-bit countdown
      timer, which is not presently used, and a periodic timer. The interval
      length for the latter is programmable via a 32-bit throttle register
      whose units are determined by a bus-period register. The periodic
      timer is used to implement both periodic and oneshot clock event
      modes; in oneshot mode the interrupt handler simply disables the timer
      as soon as it fires.
      
      Despite its device tree node representing an interrupt for the PIT,
      the actual irq generated is programmable, not hard-wired. The driver
      is responsible for programming the PIT to generate the hardware irq
      number that the DT assigns to it.
      
      On SMP configurations, J-Core provides cpu-local instances of the PIT;
      no broadcast timer is needed. This driver supports the creation of the
      necessary per-cpu clock_event_device instances.
      
      A nanosecond-resolution clocksource is provided using the J-Core "RTC"
      registers, which give a 64-bit seconds count and 32-bit nanoseconds
      that wrap every second. The driver converts these to a full-range
      32-bit nanoseconds count.
      Signed-off-by: NRich Felker <dalias@libc.org>
      Cc: Mark Rutland <mark.rutland@arm.com>
      Cc: devicetree@vger.kernel.org
      Cc: linux-sh@vger.kernel.org
      Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
      Cc: Rob Herring <robh+dt@kernel.org>
      Link: http://lkml.kernel.org/r/b591ff12cc5ebf63d1edc98da26046f95a233814.1476393790.git.dalias@libc.orgSigned-off-by: NThomas Gleixner <tglx@linutronix.de>
      9995f4f1
  8. 24 9月, 2016 1 次提交
    • S
      arm64: arch_timer: Work around QorIQ Erratum A-008585 · f6dc1576
      Scott Wood 提交于
      Erratum A-008585 says that the ARM generic timer counter "has the
      potential to contain an erroneous value for a small number of core
      clock cycles every time the timer value changes".  Accesses to TVAL
      (both read and write) are also affected due to the implicit counter
      read.  Accesses to CVAL are not affected.
      
      The workaround is to reread TVAL and count registers until successive
      reads return the same value.  Writes to TVAL are replaced with an
      equivalent write to CVAL.
      
      The workaround is to reread TVAL and count registers until successive reads
      return the same value, and when writing TVAL to retry until counter
      reads before and after the write return the same value.
      
      The workaround is enabled if the fsl,erratum-a008585 property is found in
      the timer node in the device tree.  This can be overridden with the
      clocksource.arm_arch_timer.fsl-a008585 boot parameter, which allows KVM
      users to enable the workaround until a mechanism is implemented to
      automatically communicate this information.
      
      This erratum can be found on LS1043A and LS2080A.
      Acked-by: NMarc Zyngier <marc.zyngier@arm.com>
      Signed-off-by: NScott Wood <oss@buserror.net>
      [will: renamed read macro to reflect that it's not usually unstable]
      Signed-off-by: NWill Deacon <will.deacon@arm.com>
      f6dc1576
  9. 16 9月, 2016 1 次提交
  10. 28 6月, 2016 18 次提交
  11. 09 5月, 2016 1 次提交
  12. 28 4月, 2016 1 次提交
  13. 25 2月, 2016 1 次提交
  14. 26 1月, 2016 1 次提交