1. 22 10月, 2015 1 次提交
  2. 17 10月, 2015 1 次提交
  3. 09 10月, 2015 1 次提交
  4. 03 10月, 2015 1 次提交
  5. 28 9月, 2015 1 次提交
    • S
      clk: add support for clocks provided by SCP(System Control Processor) · cd52c2a4
      Sudeep Holla 提交于
      On some ARM based systems, a separate Cortex-M based System Control
      Processor(SCP) provides the overall power, clock, reset and system
      control. System Control and Power Interface(SCPI) Message Protocol
      is defined for the communication between the Application Cores(AP)
      and the SCP.
      
      This patch adds support for the clocks provided by SCP using SCPI
      protocol.
      Signed-off-by: NSudeep Holla <sudeep.holla@arm.com>
      Reviewed-by: NStephen Boyd <sboyd@codeaurora.org>
      Cc: Mike Turquette <mturquette@baylibre.com>
      Cc: Liviu Dudau <Liviu.Dudau@arm.com>
      Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
      Cc: Jon Medhurst (Tixy) <tixy@linaro.org>
      Cc: linux-clk@vger.kernel.org
      cd52c2a4
  6. 04 6月, 2015 2 次提交
  7. 15 5月, 2015 1 次提交
  8. 13 5月, 2015 1 次提交
  9. 11 4月, 2015 1 次提交
  10. 21 1月, 2015 1 次提交
  11. 18 1月, 2015 1 次提交
  12. 07 1月, 2015 1 次提交
    • P
      rcu: Make SRCU optional by using CONFIG_SRCU · 83fe27ea
      Pranith Kumar 提交于
      SRCU is not necessary to be compiled by default in all cases. For tinification
      efforts not compiling SRCU unless necessary is desirable.
      
      The current patch tries to make compiling SRCU optional by introducing a new
      Kconfig option CONFIG_SRCU which is selected when any of the components making
      use of SRCU are selected.
      
      If we do not select CONFIG_SRCU, srcu.o will not be compiled at all.
      
         text    data     bss     dec     hex filename
         2007       0       0    2007     7d7 kernel/rcu/srcu.o
      
      Size of arch/powerpc/boot/zImage changes from
      
         text    data     bss     dec     hex filename
       831552   64180   23944  919676   e087c arch/powerpc/boot/zImage : before
       829504   64180   23952  917636   e0084 arch/powerpc/boot/zImage : after
      
      so the savings are about ~2000 bytes.
      Signed-off-by: NPranith Kumar <bobby.prani@gmail.com>
      CC: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
      CC: Josh Triplett <josh@joshtriplett.org>
      CC: Lai Jiangshan <laijs@cn.fujitsu.com>
      Signed-off-by: NPaul E. McKenney <paulmck@linux.vnet.ibm.com>
      [ paulmck: resolve conflict due to removal of arch/ia64/kvm/Kconfig. ]
      83fe27ea
  13. 29 10月, 2014 1 次提交
  14. 14 10月, 2014 1 次提交
  15. 06 10月, 2014 1 次提交
  16. 10 9月, 2014 3 次提交
  17. 02 7月, 2014 1 次提交
    • P
      clk: Add driver for Palmas clk32kg and clk32kgaudio clocks · 942d1d67
      Peter Ujfalusi 提交于
      Palmas class of devices can provide 32K clock(s) to be used by other devices
      on the board. Depending on the actual device the provided clocks can be:
      CLK32K_KG and CLK32K_KGAUDIO
      or only one:
      CLK32K_KG (TPS659039 for example)
      
      Use separate compatible flags for the two 32K clock.
      A system which needs or have only one of the 32k clock from
      Palmas will need to add node(s) for each clock as separate section
      in the dts file.
      The two compatible property is:
      "ti,palmas-clk32kg" for clk32kg clock
      "ti,palmas-clk32kgaudio" for clk32kgaudio clock
      
      Apart from the register control of the clocks - which is done via
      the clock API there is a posibility to enable the external sleep
      control. In this way the clock can be enabled/disabled on demand by the
      user of the clock.
      
      See the documentation for more details.
      Signed-off-by: NPeter Ujfalusi <peter.ujfalusi@ti.com>
      Reviewed-by: NNishanth Menon <nm@ti.com>
      Signed-off-by: NMike Turquette <mturquette@linaro.org>
      942d1d67
  18. 24 5月, 2014 1 次提交
  19. 16 5月, 2014 1 次提交
  20. 15 5月, 2014 1 次提交
  21. 19 3月, 2014 1 次提交
  22. 25 2月, 2014 1 次提交
    • A
      clk: bcm281xx: add initial clock framework support · 1f27f152
      Alex Elder 提交于
      Add code for device tree support of clocks in the BCM281xx family of
      SoCs.  Machines in this family use peripheral clocks implemented by
      "Kona" clock control units (CCUs).  (Other Broadcom SoC families use
      Kona style CCUs as well, but support for them is not yet upstream.)
      
      A BCM281xx SoC has multiple CCUs, each of which manages a set of
      clocks on the SoC.  A Kona peripheral clock is composite clock that
      may include a gate, a parent clock multiplexor, and zero, one
      or two dividers.  There is a variety of gate types, and many gates
      implement hardware-managed gating (often called "auto-gating").
      Most dividers divide their input clock signal by an integer value
      (one or more).  There are also "fractional" dividers which allow
      division by non-integer values.  To accomodate such dividers,
      clock rates and dividers are generally maintained by the code in
      "scaled" form, which allows integer and fractional dividers to
      be handled in a uniform way.
      
      If present, the gate for a Kona peripheral clock must be enabled
      when a change is made to its multiplexor or one of its dividers.
      Additionally, dividers and multiplexors have trigger registers which
      must be used whenever the divider value or selected parent clock is
      changed.  The same trigger is often used for a divider and
      multiplexor, and a BCM281xx peripheral clock occasionally has two
      triggers.
      
      The gate, dividers, and parent clock selector are treated in this
      code as "components" of a peripheral clock.  Their functionality is
      implemented directly--e.g. the common clock framework gate
      implementation is not used for a Kona peripheral clock gate.  (This
      has being considered though, and the intention is to evolve this
      code to leverage common code as much as possible.)
      
      The source code is divided into three general portions:
      
          drivers/clk/bcm/clk-kona.h
          drivers/clk/bcm/clk-kona.c
              These implement the basic Kona clock functionality,
              including the clk_ops methods and various routines to
              manipulate registers and interpret their values.  This
              includes some functions used to set clocks to a desired
              initial state (though this feature is only partially
              implemented here).
      
          drivers/clk/bcm/clk-kona-setup.c
              This contains generic run-time initialization code for
              data structures representing Kona CCUs and clocks.  This
              encapsulates the clock structure initialization that can't
              be done statically.  Note that there is a great deal of
              validity-checking code here, making explicit certain
              assumptions in the code.   This is mostly useful for adding
              new clock definitions and could possibly be disabled for
              production use.
      
          drivers/clk/bcm/clk-bcm281xx.c
              This file defines the specific CCUs used by BCM281XX family
              SoCs, as well as the specific clocks implemented by each.
              It declares a device tree clock match entry for each CCU
              defined.
      
          include/dt-bindings/clock/bcm281xx.h
              This file defines the selector (index) values used to
              identify a particular clock provided by a CCU.  It consists
              entirely of C preprocessor constants, to be used by both the
              C source and device tree source files.
      Signed-off-by: NAlex Elder <elder@linaro.org>
      Reviewed-by: NTim Kryger <tim.kryger@linaro.org>
      Reviewed-by: NMatt Porter <mporter@linaro.org>
      Acked-by: NMike Turquette <mturquette@linaro.org>
      Signed-off-by: NMatt Porter <mporter@linaro.org>
      1f27f152
  23. 17 1月, 2014 1 次提交
  24. 28 12月, 2013 1 次提交
  25. 15 12月, 2013 1 次提交
  26. 08 10月, 2013 2 次提交
  27. 09 8月, 2013 1 次提交
  28. 26 7月, 2013 1 次提交
  29. 20 6月, 2013 1 次提交
  30. 29 5月, 2013 2 次提交
  31. 16 4月, 2013 1 次提交
  32. 13 4月, 2013 1 次提交
  33. 20 3月, 2013 1 次提交
  34. 20 11月, 2012 1 次提交
  35. 30 10月, 2012 1 次提交