- 22 10月, 2015 1 次提交
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由 Scott Wood 提交于
LS2080A is the first implementation of the chassis 3 clockgen, which has a different register layout than previous chips. It is also little endian, unlike previous chips. Signed-off-by: NScott Wood <scottwood@freescale.com> Acked-by: NStephen Boyd <sboyd@codeaurora.org>
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- 17 10月, 2015 1 次提交
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由 Javier Martinez Canillas 提交于
These drivers only have runtime but no build time dependencies so can be built for testing purposes if the Kconfig COMPILE_TEST option is enabled. This is useful to have more build coverage and make sure that drivers are not affected by changes that could cause build regressions. Signed-off-by: NJavier Martinez Canillas <javier@osg.samsung.com> Acked-by: NScott Branden <sbranden@broadcom.com> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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- 09 10月, 2015 1 次提交
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由 Mike Looijmans 提交于
This patch adds the driver and devicetree documentation for the Silicon Labs SI514 clock generator chip. This is an I2C controlled oscillator capable of generating clock signals ranging from 100kHz to 250MHz. Signed-off-by: NMike Looijmans <mike.looijmans@topic.nl> [sboyd@codeaurora.org: Drop clk.h include, remove some casts] Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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- 03 10月, 2015 1 次提交
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由 Andy Shevchenko 提交于
This patch converts the code to use rational best approximation algorithm which is much more precise. Suggested-by: NStephen Boyd <sboyd@codeaurora.org> Reviewed-by: NHeikki Krogerus <heikki.krogerus@linux.intel.com> Signed-off-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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- 28 9月, 2015 1 次提交
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由 Sudeep Holla 提交于
On some ARM based systems, a separate Cortex-M based System Control Processor(SCP) provides the overall power, clock, reset and system control. System Control and Power Interface(SCPI) Message Protocol is defined for the communication between the Application Cores(AP) and the SCP. This patch adds support for the clocks provided by SCP using SCPI protocol. Signed-off-by: NSudeep Holla <sudeep.holla@arm.com> Reviewed-by: NStephen Boyd <sboyd@codeaurora.org> Cc: Mike Turquette <mturquette@baylibre.com> Cc: Liviu Dudau <Liviu.Dudau@arm.com> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Jon Medhurst (Tixy) <tixy@linaro.org> Cc: linux-clk@vger.kernel.org
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- 04 6月, 2015 2 次提交
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由 Mike Looijmans 提交于
This driver supports the TI CDCE925 programmable clock synthesizer. The chip contains two PLLs with spread-spectrum clocking support and five output dividers. The driver only supports the following setup, and uses a fixed setting for the output muxes: Y1 is derived from the input clock Y2 and Y3 derive from PLL1 Y4 and Y5 derive from PLL2 Given a target output frequency, the driver will set the PLL and divider to best approximate the desired output. Signed-off-by: NMike Looijmans <mike.looijmans@topic.nl> Signed-off-by: NMichael Turquette <mturquette@linaro.org>
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由 Bintian Wang 提交于
Add clock drivers for hi6220 SoC, this driver controls the SoC registers to supply different clocks to different IPs in the SoC. We add one divider clock for hi6220 because the divider in hi6220 also has a mask bit but it doesnot obey the rule defined by flag "CLK_DIVIDER_HIWORD_MASK", we can not get index of the mask bit by left shift fixed bits (e.g. 16 bits), so we add this divider clock to handle it. Signed-off-by: NJorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> Signed-off-by: NBintian Wang <bintian.wang@huawei.com> Acked-by: NHaojian Zhuang <haojian.zhuang@linaro.org> Reviewed-by: NZhangfei Gao <zhangfei.gao@linaro.org> Tested-by: NWill Deacon <will.deacon@arm.com> Tested-by: NTyler Baker <tyler.baker@linaro.org> Tested-by: NKevin Hilman <khilman@linaro.org> Signed-off-by: NMichael Turquette <mturquette@linaro.org>
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- 15 5月, 2015 1 次提交
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由 Stephen Boyd 提交于
Having this Kconfig sourced outside the clk menu means the option is under the "Device Drivers" menu instead of the "Common Clock Framework" menu. Move it so that the bcm clock config options are in the right place. Cc: Alex Elder <elder@linaro.org> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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- 13 5月, 2015 1 次提交
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由 Thierry Reding 提交于
The EMC clock driver uses symbols exported by the EMC driver, so it needs the corresponding dependency to avoid build breakage. Signed-off-by: NThierry Reding <treding@nvidia.com>
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- 11 4月, 2015 1 次提交
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由 Philipp Zabel 提交于
Some board designers, when running out of clock output pads, decide to (mis)use PWM output pads to provide a clock to external components. This driver supports this practice by providing an adapter between the PWM and clock bindings in the device tree. As the PWM bindings specify the period in the device tree, this is a fixed clock. Tested-by: NJanusz Uzycki <j.uzycki@elproma.com.pl> Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de> Signed-off-by: NMichael Turquette <mturquette@linaro.org>
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- 21 1月, 2015 1 次提交
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由 Tang Yuantian 提交于
Freescale introduced new ARM-based socs which using the compatible clock IP block with PowerPC-based socs'. So this driver can be used on both platforms. Updated relevant descriptions and renamed this driver to better represent its meaning and keep the function of driver untouched. Signed-off-by: NTang Yuantian <Yuantian.Tang@freescale.com> Signed-off-by: NMichael Turquette <mturquette@linaro.org>
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- 18 1月, 2015 1 次提交
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由 Max Filippov 提交于
The driver allows using CDCE706 in its default configuration recorded in EEPROM and adjusting of synthesized clocks by consumers. Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com> Signed-off-by: NMichael Turquette <mturquette@linaro.org>
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- 07 1月, 2015 1 次提交
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由 Pranith Kumar 提交于
SRCU is not necessary to be compiled by default in all cases. For tinification efforts not compiling SRCU unless necessary is desirable. The current patch tries to make compiling SRCU optional by introducing a new Kconfig option CONFIG_SRCU which is selected when any of the components making use of SRCU are selected. If we do not select CONFIG_SRCU, srcu.o will not be compiled at all. text data bss dec hex filename 2007 0 0 2007 7d7 kernel/rcu/srcu.o Size of arch/powerpc/boot/zImage changes from text data bss dec hex filename 831552 64180 23944 919676 e087c arch/powerpc/boot/zImage : before 829504 64180 23952 917636 e0084 arch/powerpc/boot/zImage : after so the savings are about ~2000 bytes. Signed-off-by: NPranith Kumar <bobby.prani@gmail.com> CC: Paul E. McKenney <paulmck@linux.vnet.ibm.com> CC: Josh Triplett <josh@joshtriplett.org> CC: Lai Jiangshan <laijs@cn.fujitsu.com> Signed-off-by: NPaul E. McKenney <paulmck@linux.vnet.ibm.com> [ paulmck: resolve conflict due to removal of arch/ia64/kvm/Kconfig. ]
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- 29 10月, 2014 1 次提交
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由 Masanari Iida 提交于
This patch fix company name's spelling typo in module descriptions and a Kconfig. Signed-off-by: NMasanari Iida <standby24x7@gmail.com> Acked-by: NRandy Dunlap <rdunlap@infradead.org> Acked-by: NChris Snook <chris.snook@gmail.com> Acked-by: NLinus Walleij <linus.walleij@linaro.org> Signed-off-by: NJiri Kosina <jkosina@suse.cz>
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- 14 10月, 2014 1 次提交
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由 Chris Zhong 提交于
This is the initial version of the RK808 PMIC. This is a power management IC for multimedia products. It provides regulators that are able to supply power to processor cores and other components. The chip provides other modules including RTC, Clockout. Signed-off-by: NChris Zhong <zyw@rock-chips.com> Reviewed-by: NDoug Anderson <dianders@chromium.org> Tested-by: NDoug Anderson <dianders@chromium.org> Tested-by: NHeiko Stuebner <heiko@sntech.de> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Samuel Ortiz <sameo@linux.intel.com> says: Cc: Alessandro Zummo <a.zummo@towertech.it> Cc: Olof Johansson <olof@lixom.net> Cc: Dmitry Torokhov <dtor@chromium.org> Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Cc: Kever Yang <kever.yang@rock-chips.com> Cc: Li Zhong <zhong@linux.vnet.ibm.com> Cc: Russell King <rmk@arm.linux.org.uk> Signed-off-by: NAndrew Morton <akpm@linux-foundation.org> Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
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- 06 10月, 2014 1 次提交
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由 Robert Jarzmik 提交于
Fix the building of pxa clock drivers so that the files are actually compiled if and only if COMMON_CLK was selected by the architecture. This prevents conflicts with mach-pxa clock legacy implementation. Signed-off-by: NRobert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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- 10 9月, 2014 3 次提交
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由 Javier Martinez Canillas 提交于
The MAX77802 PMIC has two 32.768kHz Buffered Clock Outputs with Low Jitter Mode. This patch adds support for these two clocks. Signed-off-by: NJavier Martinez Canillas <javier.martinez@collabora.co.uk> Reviewed-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Javier Martinez Canillas 提交于
Clocks drivers for Maxim PMIC are very similar so they can be converted to use the generic Maxim clock driver. Also, while being there use module_platform_driver() helper macro to eliminate more boilerplate code. Signed-off-by: NJavier Martinez Canillas <javier.martinez@collabora.co.uk> Reviewed-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Javier Martinez Canillas 提交于
Maxim Integrated Power Management ICs are very similar with regard to their clock outputs. Most of the clock drivers for these chips are duplicating code and are simpler enough that can be converted to use a generic driver to consolidate code and avoid duplication. Signed-off-by: NJavier Martinez Canillas <javier.martinez@collabora.co.uk> Reviewed-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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- 02 7月, 2014 1 次提交
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由 Peter Ujfalusi 提交于
Palmas class of devices can provide 32K clock(s) to be used by other devices on the board. Depending on the actual device the provided clocks can be: CLK32K_KG and CLK32K_KGAUDIO or only one: CLK32K_KG (TPS659039 for example) Use separate compatible flags for the two 32K clock. A system which needs or have only one of the 32k clock from Palmas will need to add node(s) for each clock as separate section in the dts file. The two compatible property is: "ti,palmas-clk32kg" for clk32kg clock "ti,palmas-clk32kgaudio" for clk32kgaudio clock Apart from the register control of the clocks - which is done via the clock API there is a posibility to enable the external sleep control. In this way the clock can be enabled/disabled on demand by the user of the clock. See the documentation for more details. Signed-off-by: NPeter Ujfalusi <peter.ujfalusi@ti.com> Reviewed-by: NNishanth Menon <nm@ti.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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- 24 5月, 2014 1 次提交
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由 Krzysztof Kozlowski 提交于
This patch adds support for S2MPS14 PMIC clocks (BT and AP) to the s2mps11 clock driver. Signed-off-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com> Cc: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: NYadwinder Singh Brar <yadi.brar@samsung.com> Reviewed-by: NTomasz Figa <t.figa@samsung.com> Acked-by: NMike Turquette <mturquette@linaro.org> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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- 16 5月, 2014 1 次提交
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由 Pawel Moll 提交于
Move the Kconfig entry for Versatile (& Express) clock drivers into a separate file and add individual options for sp810 and vexpress_osc drivers, as they are optional in some configurations and may have separate dependencies. Signed-off-by: NPawel Moll <pawel.moll@arm.com> Acked-by: NMike Turquette <mturquette@linaro.org>
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- 15 5月, 2014 1 次提交
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由 Pankaj Dubey 提交于
This patch adds new Kconfig file for adding new COMMON_CLK_SAMSUNG option. Samsung platforms can select this for using common clock infrastructure. CC: Mike Turquette <mturquette@linaro.org> Signed-off-by: NPankaj Dubey <pankaj.dubey@samsung.com> Signed-off-by: NTomasz Figa <t.figa@samsung.com>
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- 19 3月, 2014 1 次提交
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由 Tushar Behera 提交于
Since clock operation within S2MPS11 and S5M8767 are similar, we can support both the devices within a single driver. Signed-off-by: NTushar Behera <tushar.behera@linaro.org> Reviewed-by: NTomasz Figa <t.figa@samsung.com> Reviewed-by: NYadwinder Singh Brar <yadi.brar@samsung.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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- 25 2月, 2014 1 次提交
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由 Alex Elder 提交于
Add code for device tree support of clocks in the BCM281xx family of SoCs. Machines in this family use peripheral clocks implemented by "Kona" clock control units (CCUs). (Other Broadcom SoC families use Kona style CCUs as well, but support for them is not yet upstream.) A BCM281xx SoC has multiple CCUs, each of which manages a set of clocks on the SoC. A Kona peripheral clock is composite clock that may include a gate, a parent clock multiplexor, and zero, one or two dividers. There is a variety of gate types, and many gates implement hardware-managed gating (often called "auto-gating"). Most dividers divide their input clock signal by an integer value (one or more). There are also "fractional" dividers which allow division by non-integer values. To accomodate such dividers, clock rates and dividers are generally maintained by the code in "scaled" form, which allows integer and fractional dividers to be handled in a uniform way. If present, the gate for a Kona peripheral clock must be enabled when a change is made to its multiplexor or one of its dividers. Additionally, dividers and multiplexors have trigger registers which must be used whenever the divider value or selected parent clock is changed. The same trigger is often used for a divider and multiplexor, and a BCM281xx peripheral clock occasionally has two triggers. The gate, dividers, and parent clock selector are treated in this code as "components" of a peripheral clock. Their functionality is implemented directly--e.g. the common clock framework gate implementation is not used for a Kona peripheral clock gate. (This has being considered though, and the intention is to evolve this code to leverage common code as much as possible.) The source code is divided into three general portions: drivers/clk/bcm/clk-kona.h drivers/clk/bcm/clk-kona.c These implement the basic Kona clock functionality, including the clk_ops methods and various routines to manipulate registers and interpret their values. This includes some functions used to set clocks to a desired initial state (though this feature is only partially implemented here). drivers/clk/bcm/clk-kona-setup.c This contains generic run-time initialization code for data structures representing Kona CCUs and clocks. This encapsulates the clock structure initialization that can't be done statically. Note that there is a great deal of validity-checking code here, making explicit certain assumptions in the code. This is mostly useful for adding new clock definitions and could possibly be disabled for production use. drivers/clk/bcm/clk-bcm281xx.c This file defines the specific CCUs used by BCM281XX family SoCs, as well as the specific clocks implemented by each. It declares a device tree clock match entry for each CCU defined. include/dt-bindings/clock/bcm281xx.h This file defines the selector (index) values used to identify a particular clock provided by a CCU. It consists entirely of C preprocessor constants, to be used by both the C source and device tree source files. Signed-off-by: NAlex Elder <elder@linaro.org> Reviewed-by: NTim Kryger <tim.kryger@linaro.org> Reviewed-by: NMatt Porter <mporter@linaro.org> Acked-by: NMike Turquette <mturquette@linaro.org> Signed-off-by: NMatt Porter <mporter@linaro.org>
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- 17 1月, 2014 1 次提交
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由 Stephen Boyd 提交于
Add a clock type that associates a regmap pointer and some enable/disable bits with a clk_hw struct. This will be the struct that a hw specific implementation wraps if it wants to use the regmap helper functions. Signed-off-by: NStephen Boyd <sboyd@codeaurora.org> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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- 28 12月, 2013 1 次提交
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由 Mike Turquette 提交于
Populate ${DEBUGS_MOUNT_POINT}/clk if CONFIG_DEBUG_FS is set. This eliminates the extra (annoying) step of enabling the config option manually. Signed-off-by: NMike Turquette <mturquette@linaro.org>
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- 15 12月, 2013 1 次提交
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由 Soren Brinkmann 提交于
Add a driver for SILabs 570, 571, 598, 599 programmable oscillators. The devices generate low-jitter clock signals and are reprogrammable via an I2C interface. Reviewed-by: NGuenter Roeck <linux@roeck-us.net> Signed-off-by: NSoren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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- 08 10月, 2013 2 次提交
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由 Santosh Shilimkar 提交于
Now build the keystone common clock drivers. The build is made conditional based on COMMON_CLK_KEYSTONE Signed-off-by: NSantosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Loc Ho 提交于
clk: Add APM X-Gene SoC clock driver for reference, PLL, and device clocks. Signed-off-by: NLoc Ho <lho@apm.com> Signed-off-by: NKumar Sankaran <ksankaran@apm.com> Signed-off-by: NVinayak Kale <vkale@apm.com> Signed-off-by: NFeng Kan <fkan@apm.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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- 09 8月, 2013 1 次提交
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由 Yadwinder Singh Brar 提交于
This patch adds support to register three(AP/CP/BT) buffered 32.768 KHz outputs of mfd-s2mps11 with common clock framework. Signed-off-by: NYadwinder Singh Brar <yadi.brar@samsung.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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- 26 7月, 2013 1 次提交
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由 Peter Meerwald 提交于
Signed-off-by: NPeter Meerwald <pmeerw@pmeerw.net> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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- 20 6月, 2013 1 次提交
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由 Pawel Moll 提交于
The new arm64 architecture has no idea of platform or machine, so it doesn't have to define ARCH_VEXPRESS configuration option at all. To allow user to select the drivers at all, make it depend on ARM64 as well. Signed-off-by: NPawel Moll <pawel.moll@arm.com> Acked-by: NCatalin Marinas <catalin.marinas@arm.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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- 29 5月, 2013 2 次提交
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由 Sebastian Hesselbarth 提交于
With of_clk_provider stubs for CONFIG_OF not set, we can now also enable clk-si5351 on those architectures. Signed-off-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Tang Yuantian 提交于
This adds the clock driver for Freescale PowerPC corenet series SoCs using common clock infrastructure. Signed-off-by: NTang Yuantian <Yuantian.Tang@freescale.com> Signed-off-by: NLi Yang <leoli@freescale.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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- 16 4月, 2013 1 次提交
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由 Sebastian Hesselbarth 提交于
Calling clk-si5351 driver non-OF ready was too early. This patch makes clk-si5351 depend on CONFIG_OF again, until things get sorted out. Signed-off-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Reported-by: NStephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: NMike Turquette <mturquette@linaro.org> [mturquette@linaro.org: fixed spelling of Stephen's name]
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- 13 4月, 2013 1 次提交
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由 Sebastian Hesselbarth 提交于
This patch adds a common clock driver for Silicon Labs Si5351a/b/c i2c programmable clock generators. Currently, the driver does not support VXCO feature of si5351b. Passing platform_data or DT bindings selectively allows to overwrite stored Si5351 configuration which is very helpful for clock generators with empty eeprom configuration. Corresponding device tree binding documentation is also added. Signed-off-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by: NDaniel Mack <zonque@gmail.com> Acked-by: NGuenter Roeck <linux@roeck-us.net> Tested-by: NMichal Bachraty <michal.bachraty@streamunlimited.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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- 20 3月, 2013 1 次提交
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由 Lars-Peter Clausen 提交于
This driver adds support for the AXI clkgen pcore to the common clock framework. The AXI clkgen pcore is a AXI front-end to the MMCM_ADV frequency synthesizer commonly found in Xilinx FPGAs. The AXI clkgen pcore is used in Analog Devices' reference designs targeting Xilinx FPGAs. Signed-off-by: NLars-Peter Clausen <lars@metafoo.de> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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- 20 11月, 2012 1 次提交
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由 Sebastian Hesselbarth 提交于
This driver allows to provide DT clocks for core clocks found on Marvell Kirkwood, Dove & 370/XP SoCs. The core clock frequencies and ratios are determined by decoding the Sample-At-Reset registers. Although technically correct, using a divider of 0 will lead to div_by_zero panic. Let's use a ratio of 0/1 instead to fail later with a zero clock. Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: NAndrew Lunn <andrew@lunn.ch> Tested-by Gregory CLEMENT <gregory.clement@free-electrons.com>
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- 30 10月, 2012 1 次提交
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由 Pawel Moll 提交于
This patch adds a DT and non-DT based implementation of the common clock infrastructure for Versatile Express platform. It registers (statically or using DT) all required fixed clocks, initialises motherboard's SP810 cell (that provides clocks for SP804 timers) and explicitly registers VE "osc" driver, to make the clock generators available early. Signed-off-by: NPawel Moll <pawel.moll@arm.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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