1. 23 10月, 2008 2 次提交
  2. 23 7月, 2008 1 次提交
    • V
      x86: consolidate header guards · 77ef50a5
      Vegard Nossum 提交于
      This patch is the result of an automatic script that consolidates the
      format of all the headers in include/asm-x86/.
      
      The format:
      
      1. No leading underscore. Names with leading underscores are reserved.
      2. Pathname components are separated by two underscores. So we can
         distinguish between mm_types.h and mm/types.h.
      3. Everything except letters and numbers are turned into single
         underscores.
      Signed-off-by: NVegard Nossum <vegard.nossum@gmail.com>
      77ef50a5
  3. 30 1月, 2008 7 次提交
  4. 19 12月, 2007 1 次提交
  5. 18 10月, 2007 3 次提交
  6. 13 10月, 2007 2 次提交
    • N
      x86: optimise barriers · b6c7347f
      Nick Piggin 提交于
      According to latest memory ordering specification documents from Intel
      and AMD, both manufacturers are committed to in-order loads from
      cacheable memory for the x86 architecture.  Hence, smp_rmb() may be a
      simple barrier.
      
      Also according to those documents, and according to existing practice in
      Linux (eg.  spin_unlock doesn't enforce ordering), stores to cacheable
      memory are visible in program order too.  Special string stores are safe
      -- their constituent stores may be out of order, but they must complete
      in order WRT surrounding stores.  Nontemporal stores to WB memory can go
      out of order, and so they should be fenced explicitly to make them
      appear in-order WRT other stores.  Hence, smp_wmb() may be a simple
      barrier.
      
          http://developer.intel.com/products/processor/manuals/318147.pdf
          http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/24593.pdf
      
      In userspace microbenchmarks on a core2 system, fence instructions range
      anywhere from around 15 cycles to 50, which may not be totally
      insignificant in performance critical paths (code size will go down
      too).
      
      However the primary motivation for this is to have the canonical barrier
      implementation for x86 architecture.
      
      smp_rmb on buggy pentium pros remains a locked op, which is apparently
      required.
      Signed-off-by: NNick Piggin <npiggin@suse.de>
      Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      b6c7347f
    • N
      x86: fix IO write barrier · 4071c718
      Nick Piggin 提交于
      wmb() on x86 must always include a barrier, because stores can go out of
      order in many cases when dealing with devices (eg. WC memory).
      Signed-off-by: NNick Piggin <npiggin@suse.de>
      Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      4071c718
  7. 11 10月, 2007 1 次提交
  8. 23 7月, 2007 1 次提交
  9. 22 7月, 2007 1 次提交
  10. 20 7月, 2007 1 次提交
  11. 10 5月, 2007 1 次提交
    • R
      rename thread_info to stack · f7e4217b
      Roman Zippel 提交于
      This finally renames the thread_info field in task structure to stack, so that
      the assumptions about this field are gone and archs have more freedom about
      placing the thread_info structure.
      
      Nonbroken archs which have a proper thread pointer can do the access to both
      current thread and task structure via a single pointer.
      
      It'll allow for a few more cleanups of the fork code, from which e.g.  ia64
      could benefit.
      Signed-off-by: NRoman Zippel <zippel@linux-m68k.org>
      [akpm@linux-foundation.org: build fix]
      Cc: Richard Henderson <rth@twiddle.net>
      Cc: Ivan Kokshaysky <ink@jurassic.park.msu.ru>
      Cc: Russell King <rmk@arm.linux.org.uk>
      Cc: Ian Molton <spyro@f2s.com>
      Cc: Haavard Skinnemoen <hskinnemoen@atmel.com>
      Cc: Mikael Starvik <starvik@axis.com>
      Cc: David Howells <dhowells@redhat.com>
      Cc: Yoshinori Sato <ysato@users.sourceforge.jp>
      Cc: "Luck, Tony" <tony.luck@intel.com>
      Cc: Hirokazu Takata <takata@linux-m32r.org>
      Cc: Geert Uytterhoeven <geert@linux-m68k.org>
      Cc: Roman Zippel <zippel@linux-m68k.org>
      Cc: Greg Ungerer <gerg@uclinux.org>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: Paul Mackerras <paulus@samba.org>
      Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
      Cc: Heiko Carstens <heiko.carstens@de.ibm.com>
      Cc: Martin Schwidefsky <schwidefsky@de.ibm.com>
      Cc: Paul Mundt <lethal@linux-sh.org>
      Cc: Kazumoto Kojima <kkojima@rr.iij4u.or.jp>
      Cc: Richard Curnow <rc@rc0.org.uk>
      Cc: William Lee Irwin III <wli@holomorphy.com>
      Cc: "David S. Miller" <davem@davemloft.net>
      Cc: Jeff Dike <jdike@addtoit.com>
      Cc: Paolo 'Blaisorblade' Giarrusso <blaisorblade@yahoo.it>
      Cc: Miles Bader <uclinux-v850@lsi.nec.co.jp>
      Cc: Andi Kleen <ak@muc.de>
      Cc: Chris Zankel <chris@zankel.net>
      Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
      Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      f7e4217b
  12. 09 5月, 2007 3 次提交
  13. 03 5月, 2007 1 次提交
    • G
      [PATCH] x86-64: Remove duplicated code for reading control registers · fbc16f2c
      Glauber de Oliveira Costa 提交于
      On Tue, Mar 13, 2007 at 05:33:09AM -0700, Randy.Dunlap wrote:
      > On Tue, 13 Mar 2007, Glauber de Oliveira Costa wrote:
      >
      > > Tiny cleanup:
      > >
      > > In x86_64, the same functions for reading cr3 and writing cr{3,4} are
      > > defined in tlbflush.h and system.h, whith just a name change.
      > > The only difference is the clobbering of memory, which seems a safe, and
      > > even needed change for the write_cr4. This patch removes the duplicate.
      > > write_cr3() is moved to system.h for consistency.
      >
      > missing patch.....
      >
      thanks. Attached now
      
      --
      Glauber de Oliveira Costa
      Red Hat Inc.
      "Free as in Freedom"
      Signed-off-by: NAndi Kleen <ak@suse.de>
      fbc16f2c
  14. 26 9月, 2006 1 次提交
  15. 15 7月, 2006 1 次提交
    • S
      [PATCH] remove set_wmb - arch removal · 52393ccc
      Steven Rostedt 提交于
      set_wmb should not be used in the kernel because it just confuses the
      code more and has no benefit.  Since it is not currently used in the
      kernel this patch removes it so that new code does not include it.
      
      All archs define set_wmb(var, value) to do { var = value; wmb(); }
      while(0) except ia64 and sparc which use a mb() instead.  But this is
      still moot since it is not used anyway.
      
      Hasn't been tested on any archs but x86 and x86_64 (and only compiled
      tested)
      Signed-off-by: NSteven Rostedt <rostedt@goodmis.org>
      Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      52393ccc
  16. 04 7月, 2006 1 次提交
  17. 27 6月, 2006 1 次提交
    • G
      [PATCH] x86_64: x86_64 version of the smp alternative patch. · d167a518
      Gerd Hoffmann 提交于
      Changes are largely identical to the i386 version:
      
       * alternative #define are moved to the new alternative.h file.
       * one new elf section with pointers to the lock prefixes which can be
         nop'ed out for non-smp.
       * two new elf sections simliar to the "classic" alternatives to
         replace SMP code with simpler UP code.
       * fixup headers to use alternative.h instead of defining their own
         LOCK / LOCK_PREFIX macros.
      
      The patch reuses the i386 version of the alternatives code to avoid code
      duplication.  The code in alternatives.c was shuffled around a bit to
      reduce the number of #ifdefs needed.  It also got some tweaks needed for
      x86_64 (vsyscall page handling) and new features (noreplacement option
      which was x86_64 only up to now).  Debug printk's are changed from
      compile-time to runtime.
      
      Loosely based on a early version from Bastian Blank <waldi@debian.org>
      Signed-off-by: NGerd Hoffmann <kraxel@suse.de>
      Signed-off-by: NAndi Kleen <ak@suse.de>
      Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      d167a518
  18. 26 4月, 2006 1 次提交
  19. 26 3月, 2006 1 次提交
  20. 06 2月, 2006 1 次提交
  21. 17 1月, 2006 1 次提交
  22. 13 1月, 2006 1 次提交
  23. 12 1月, 2006 4 次提交
  24. 07 1月, 2006 1 次提交
  25. 13 9月, 2005 1 次提交