1. 31 10月, 2017 5 次提交
  2. 28 10月, 2017 1 次提交
  3. 27 10月, 2017 3 次提交
  4. 25 10月, 2017 2 次提交
    • V
      drm/i915: Adjust system agent voltage on CNL if required by DDI ports · 53e9bf5e
      Ville Syrjälä 提交于
      On CNL we may need to bump up the system agent voltage not only due
      to CDCLK but also when driving DDI port with a sufficiently high clock.
      To that end start tracking the minimum acceptable voltage for each crtc.
      We do the tracking via crtcs because we don't have any kind of encoder
      state. Also there's no downside to doing it this way, and it matches how
      we track cdclk requirements on account of pixel rate.
      
      v2: Allow disabled crtcs to use the min voltage
          Add IS_CNL check to intel_ddi_compute_min_voltage() since
          we're using CNL specific values there
          s/intel_compute_min_voltage/cnl_compute_min_voltage/ since
          the function makes hw specific assumptions about the voltage
          values
      v3: Drop the test hack leftovers from skl_modeset_calc_cdclk()
      v4: s/voltage/voltage_level/ (Rodrigo)
          Replace DPLL DVFS FIXMEs with an explanation why we don't
          do anything there (Rodrigo)
      
      Cc: Mika Kahola <mika.kahola@intel.com>
      Cc: Manasi Navare <manasi.d.navare@intel.com>
      Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
      Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com>
      Reviewed-by: NRodrigo Vivi <rodrigo.vivi@intel.com>
      Link: https://patchwork.freedesktop.org/patch/msgid/20171024095216.1638-9-ville.syrjala@linux.intel.com
      53e9bf5e
    • R
      drm/i915/cnl: Force DDI_A_4_LANES when needed. · 436009b5
      Rodrigo Vivi 提交于
      As we faced in BXT, on CNL DDI_A_4_LANES is not
      set as expected when system is boot with multiple
      monitors connected. This result in wrong lane
      setup impacting the max data rate available and
      consequently blocking modeset on eDP, resulting
      in a blank screen.
      
      Most of CNL SKUs don't support DDI-E.
      The only SKU that supports DDI-E is the same
      that supports the full A/E split called DDI-F.
      
      Also when DDI-F is used DDI-E cannot be used because
      they share Interrupts. So DDI-E is almost useless.
      Anyways let's consider this is possible and rely on
      VBT for that.
      
      This patch was initialy start by Clint, but required
      many changes including full commit message. So
      Credits entirely to Clint for finding this.
      
      v2: Extract all messy conditions into a helper function
          as suggested by Ville.
          Along with simplification I removed the debug
          message on the working case since now all conditions
          are grouped.
      v3: Split the conditions even more as suggested by Ville.
          Get's cleaner and easier to add new cases in the
          future.
      Suggested-by: NClint Taylor <clinton.a.taylor@intel.com>
      Cc: Clint Taylor <clinton.a.taylor@intel.com>
      Cc: Mika Kahola <mika.kahola@intel.com>
      Cc: Jani Nikula <jani.nikula@intel.com>
      Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
      Signed-off-by: NRodrigo Vivi <rodrigo.vivi@intel.com>
      Reviewed-by: NVille Syrjälä <ville.syrjala@linux.intel.com>
      Link: https://patchwork.freedesktop.org/patch/msgid/20171023173920.22890-1-rodrigo.vivi@intel.com
      436009b5
  5. 21 10月, 2017 1 次提交
  6. 19 10月, 2017 10 次提交
  7. 17 10月, 2017 1 次提交
  8. 14 10月, 2017 9 次提交
  9. 10 10月, 2017 1 次提交
  10. 06 10月, 2017 1 次提交
  11. 05 10月, 2017 2 次提交
  12. 03 10月, 2017 1 次提交
    • I
      drm/i915: Fix DDI PHY init if it was already on · e19c1eb8
      Imre Deak 提交于
      The common lane power down flag of a DPIO PHY has a funky semantic:
      after the initial enabling of the PHY (so from a disabled state) this
      flag will be clear. It will be set only after the PHY will be used for
      the first time (for instance due to enabling the corresponding pipe) and
      then become unused (due to disabling the pipe). During the initial PHY
      enablement we don't know which of the above phases we are in, so move
      the check for the flag where this is known, the HW readout code. This is
      where the rest of lane power down status checks are done anyway.
      
      This fixes at least a problem on GLK where after module reloading, the
      common lane power down flag of PHY1 is set, but the PHY is actually
      powered-on and properly set up. The GRC readout code for other PHYs will
      hence think that PHY1 is not powered initially and disable it after the
      GRC readout. This will cause the AUX power well related to PHY1 to get
      disabled in a stuck state, timing out when we try to enable it later.
      
      Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
      Fixes: e93da0a0 ("drm/i915/bxt: Sanitiy check the PHY lane power down status")
      Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102777Signed-off-by: NImre Deak <imre.deak@intel.com>
      Reviewed-by: NRodrigo Vivi <rodrigo.vivi@intel.com>
      Link: https://patchwork.freedesktop.org/patch/msgid/20171002135307.26117-1-imre.deak@intel.com
      e19c1eb8
  13. 20 9月, 2017 3 次提交