1. 12 7月, 2008 21 次提交
    • S
      x64, x2apic/intr-remap: code re-structuring, to be used by both DMA and Interrupt remapping · 1886e8a9
      Suresh Siddha 提交于
      Allocate the iommu during the parse of DMA remapping hardware
      definition structures. And also, introduce routines for device
      scope initialization which will be explicitly called during
      dma-remapping initialization.
      
      These will be used for enabling interrupt remapping separately from the
      existing DMA-remapping enabling sequence.
      Signed-off-by: NSuresh Siddha <suresh.b.siddha@intel.com>
      Cc: akpm@linux-foundation.org
      Cc: arjan@linux.intel.com
      Cc: andi@firstfloor.org
      Cc: ebiederm@xmission.com
      Cc: jbarnes@virtuousgeek.org
      Cc: steiner@sgi.com
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      1886e8a9
    • S
      x64, x2apic/intr-remap: fix the need for sequential array allocation of iommus · c42d9f32
      Suresh Siddha 提交于
      Clean up the intel-iommu code related to deferred iommu flush logic. There is
      no need to allocate all the iommu's as a sequential array.
      
      This will be used later in the interrupt-remapping patch series to
      allocate iommu much early and individually for each device remapping
      hardware unit.
      Signed-off-by: NSuresh Siddha <suresh.b.siddha@intel.com>
      Cc: akpm@linux-foundation.org
      Cc: arjan@linux.intel.com
      Cc: andi@firstfloor.org
      Cc: ebiederm@xmission.com
      Cc: jbarnes@virtuousgeek.org
      Cc: steiner@sgi.com
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      c42d9f32
    • S
      x64, x2apic/intr-remap: Intel vt-d, IOMMU code reorganization · e61d98d8
      Suresh Siddha 提交于
      code reorganization of the generic Intel vt-d parsing related routines and linux
      iommu routines specific to Intel vt-d.
      
      drivers/pci/dmar.c	now contains the generic vt-d parsing related routines
      drivers/pci/intel_iommu.c contains the iommu routines specific to vt-d
      Signed-off-by: NSuresh Siddha <suresh.b.siddha@intel.com>
      Cc: akpm@linux-foundation.org
      Cc: arjan@linux.intel.com
      Cc: andi@firstfloor.org
      Cc: ebiederm@xmission.com
      Cc: jbarnes@virtuousgeek.org
      Cc: steiner@sgi.com
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      e61d98d8
    • I
      Merge branch 'x86/core' into x86/x2apic · 1ba89386
      Ingo Molnar 提交于
      1ba89386
    • I
      Merge branch 'linus' into x86/core · ae94b807
      Ingo Molnar 提交于
      Conflicts:
      
      	arch/x86/mm/ioremap.c
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      ae94b807
    • R
      x86_64: fix delayed signals · eca91e78
      Roland McGrath 提交于
      On three of the several paths in entry_64.S that call
      do_notify_resume() on the way back to user mode, we fail to properly
      check again for newly-arrived work that requires another call to
      do_notify_resume() before going to user mode.  These paths set the
      mask to check only _TIF_NEED_RESCHED, but this is wrong.  The other
      paths that lead to do_notify_resume() do this correctly already, and
      entry_32.S does it correctly in all cases.
      
      All paths back to user mode have to check all the _TIF_WORK_MASK
      flags at the last possible stage, with interrupts disabled.
      Otherwise, we miss any flags (TIF_SIGPENDING for example) that were
      set any time after we entered do_notify_resume().  More work flags
      can be set (or left set) synchronously inside do_notify_resume(), as
      TIF_SIGPENDING can be, or asynchronously by interrupts or other CPUs
      (which then send an asynchronous interrupt).
      
      There are many different scenarios that could hit this bug, most of
      them races.  The simplest one to demonstrate does not require any
      race: when one signal has done handler setup at the check before
      returning from a syscall, and there is another signal pending that
      should be handled.  The second signal's handler should interrupt the
      first signal handler before it actually starts (so the interrupted PC
      is still at the handler's entry point).  Instead, it runs away until
      the next kernel entry (next syscall, tick, etc).
      
      This test behaves correctly on 32-bit kernels, and fails on 64-bit
      (either 32-bit or 64-bit test binary).  With this fix, it works.
      
          #define _GNU_SOURCE
          #include <stdio.h>
          #include <signal.h>
          #include <string.h>
          #include <sys/ucontext.h>
      
          #ifndef REG_RIP
          #define REG_RIP REG_EIP
          #endif
      
          static sig_atomic_t hit1, hit2;
      
          static void
          handler (int sig, siginfo_t *info, void *ctx)
          {
            ucontext_t *uc = ctx;
      
            if ((void *) uc->uc_mcontext.gregs[REG_RIP] == &handler)
              {
                if (sig == SIGUSR1)
                  hit1 = 1;
                else
                  hit2 = 1;
              }
      
            printf ("%s at %#lx\n", strsignal (sig),
                    uc->uc_mcontext.gregs[REG_RIP]);
          }
      
          int
          main (void)
          {
            struct sigaction sa;
            sigset_t set;
      
            sigemptyset (&sa.sa_mask);
            sa.sa_flags = SA_SIGINFO;
            sa.sa_sigaction = &handler;
      
            if (sigaction (SIGUSR1, &sa, NULL)
                || sigaction (SIGUSR2, &sa, NULL))
              return 2;
      
            sigemptyset (&set);
            sigaddset (&set, SIGUSR1);
            sigaddset (&set, SIGUSR2);
            if (sigprocmask (SIG_BLOCK, &set, NULL))
              return 3;
      
            printf ("main at %p, handler at %p\n", &main, &handler);
      
            raise (SIGUSR1);
            raise (SIGUSR2);
      
            if (sigprocmask (SIG_UNBLOCK, &set, NULL))
              return 4;
      
            if (hit1 + hit2 == 1)
              {
                puts ("PASS");
                return 0;
              }
      
            puts ("FAIL");
            return 1;
          }
      Signed-off-by: NRoland McGrath <roland@redhat.com>
      Cc: Andrew Morton <akpm@linux-foundation.org>
      Cc: Linus Torvalds <torvalds@linux-foundation.org>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      eca91e78
    • R
      x86: remove conflicting nx6325 and nx6125 quirks · da1f29f5
      Rafael J. Wysocki 提交于
      We have two conflicting DMA-based quirks in there for the same set of
      boxes (HP nx6325 and nx6125) and one of them actually breaks my box.
      
      So remove the extra code.
      Signed-off-by: NRafael J. Wysocki <rjw@sisk.pl>
      Cc: Stephen Rothwell <sfr@canb.auug.org.au>
      Cc: =?iso-8859-1?q?T=F6r=F6k_Edwin?= <edwintorok@gmail.com>
      Cc: Vegard Nossum <vegard.nossum@gmail.com>
      Cc: Andreas Herrmann <andreas.herrmann3@amd.com>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      da1f29f5
    • L
      a26929fb
    • M
      [PATCH] IPMI: return correct value from ipmi_write · 3976df9b
      Mark Rustad 提交于
      This patch corrects the handling of write operations to the IPMI watchdog
      to work as intended by returning the number of characters actually
      processed. Without this patch, an "echo V >/dev/watchdog" enables the
      watchdog if IPMI is providing the watchdog function.
      Signed-off-by: NMark Rustad <MRustad@gmail.com>
      Signed-off-by: NCorey Minyard <cminyard@mvista.com>
      Signed-off-by: NWim Van Sebroeck <wim@iguana.be>
      3976df9b
    • I
      Merge branch 'x86/generalize-visws' into x86/core · 6c82a000
      Ingo Molnar 提交于
      6c82a000
    • M
      x86: Recover timer_ack lost in the merge of the NMI watchdog · 5b4d2386
      Maciej W. Rozycki 提交于
      In the course of the recent unification of the NMI watchdog an assignment
      to timer_ack to switch off unnecesary POLL commands to the 8259A in the
      case of a watchdog failure has been accidentally removed.  The statement
      used to be limited to the 32-bit variation as since the rewrite of the
      timer code it has been relevant for the 82489DX only.  This change brings
      it back.
      Signed-off-by: NMaciej W. Rozycki <macro@linux-mips.org>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      5b4d2386
    • M
      x86: I/O APIC: Never configure IRQ2 · af174783
      Maciej W. Rozycki 提交于
      There is no such entity as ISA IRQ2.  The ACPI spec does not make it
      explicitly clear, but does not preclude it either -- all it says is ISA
      legacy interrupts are identity mapped by default (subject to overrides),
      but it does not state whether IRQ2 exists or not.  As a result if there is
      no IRQ0 override, then IRQ2 is normally initialised as an ISA interrupt,
      which implies an edge-triggered line, which is unmasked by default as this
      is what we do for edge-triggered I/O APIC interrupts so as not to miss an
      edge.
      
      To the best of my knowledge it is useless, as IRQ2 has not been in use
      since the PC/AT as back then it was taken by the 8259A cascade interrupt
      to the slave, with the line position in the slot rerouted to newly-created
      IRQ9.  No device could thus make use of this line with the pair of 8259A
      chips.  Now in theory INTIN2 of the I/O APIC may be usable, but the
      interrupt of the device wired to it would not be available in the PIC mode
      at all, so I seriously doubt if anybody decided to reuse it for a regular
      device.
      
      However there are two common uses of INTIN2.  One is for IRQ0, with an
      ACPI interrupt override (or its equivalent in the MP table).  But in this
      case IRQ2 is gone entirely with INTIN0 left vacant.  The other one is for
      an 8959A ExtINTA cascade.  In this case IRQ0 goes to INTIN0 and if ACPI is
      used INTIN2 is assumed to be IRQ2 (there is no override and ACPI has no
      way to report ExtINTA interrupts).  This is where a problem happens.
      
      The problem is INTIN2 is configured as a native APIC interrupt, with a
      vector assigned and the mask cleared.  And the line may indeed get active
      and inject interrupts if the master 8959A has its timer interrupt enabled
      (it might happen for other interrupts too, but they are normally masked in
      the process of rerouting them to the I/O APIC).  There are two cases where
      it will happen:
      
      * When the I/O APIC NMI watchdog is enabled.  This is actually a misnomer
        as the watchdog pulses are delivered through the 8259A to the LINT0
        inputs of all the local APICs in the system.  The implication is the
        output of the master 8259A goes high and low repeatedly, signalling
        interrupts to INTIN2 which is enabled too!
      
        [The origin of the name is I think for a brief period during the
        development we had a capability in our code to configure the watchdog to
        use an I/O APIC input; that would be INTIN2 in this scenario.]
      
      * When the native route of IRQ0 via INTIN0 fails for whatever reason -- as
        it happens with the system considered here.  In this scenario the timer
        pulse is delivered through the 8259A to LINT0 input of the local APIC of
        the bootstrap processor, quite similarly to how is done for the watchdog
        described above.  The result is, again, INTIN2 receives these pulses
        too.  Rafael's system used to escape this scenario, because an incorrect
        IRQ0 override would occupy INTIN2 and prevent it from being unmasked.
      
      My conclusion is IRQ2 should be excluded from configuration in all the
      cases and the current exception for ACPI systems should be lifted.  The
      reason being the exception not only being useless, but harmful as well.
      Signed-off-by: NMaciej W. Rozycki <macro@linux-mips.org>
      Cc: "Rafael J. Wysocki" <rjw@sisk.pl>
      Cc: Matthew Garrett <mjg59@srcf.ucam.org>
      Cc: Andreas Herrmann <andreas.herrmann3@amd.com>
      Cc: Stephen Rothwell <sfr@canb.auug.org.au>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      af174783
    • M
      x86: L-APIC: Always fully configure IRQ0 · c88ac1df
      Maciej W. Rozycki 提交于
      Unlike the 32-bit one, the 64-bit variation of the LVT0 setup code for
      the "8259A Virtual Wire" through the local APIC timer configuration does
      not fully configure the relevant irq_chip structure.  Instead it relies on
      the preceding I/O APIC code to have set it up, which does not happen if
      the I/O APIC variants have not been tried.
      
      The patch includes corresponding changes to the 32-bit variation too
      which make them both the same, barring a small syntactic difference
      involving sequence of functions in the source.  That should work as an aid
      with the upcoming merge.
      Signed-off-by: NMaciej W. Rozycki <macro@linux-mips.org>
      Cc: "Rafael J. Wysocki" <rjw@sisk.pl>
      Cc: Matthew Garrett <mjg59@srcf.ucam.org>
      Cc: Andreas Herrmann <andreas.herrmann3@amd.com>
      Cc: Stephen Rothwell <sfr@canb.auug.org.au>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      c88ac1df
    • M
      x86: L-APIC: Set IRQ0 as edge-triggered · 1baea6e2
      Maciej W. Rozycki 提交于
       IRQ0 is edge-triggered, but the "8259A Virtual Wire" through the local
      APIC configuration in the 32-bit version uses the "fasteoi" handler
      suitable for level-triggered APIC interrupt.  Rewrite code so that the
      "edge" handler is used.  The 64-bit version uses different code and is
      unaffected.
      Signed-off-by: NMaciej W. Rozycki <macro@linux-mips.org>
      Cc: "Rafael J. Wysocki" <rjw@sisk.pl>
      Cc: Matthew Garrett <mjg59@srcf.ucam.org>
      Cc: Andreas Herrmann <andreas.herrmann3@amd.com>
      Cc: Stephen Rothwell <sfr@canb.auug.org.au>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      1baea6e2
    • G
      x86: merge dwarf2 headers · 392a0fc9
      Glauber Costa 提交于
      Merge dwarf2_32.h and dwarf2_64.h into dwarf2.h.
      Signed-off-by: NGlauber Costa <gcosta@redhat.com>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      392a0fc9
    • G
      x86: use AS_CFI instead of UNWIND_INFO · d73a731a
      Glauber Costa 提交于
      In dwarf2_32.h, test for CONFIG_AS_CFI instead of
      CONFIG_UNWIND_INFO. Turns out that searching for UNWIND_INFO
      returns no match in any Kconfig or Makefile, so we're really
      just throwing everything away regarding dwarf frames for i386.
      
      The test that generates CONFIG_AS_CFI does not have anything
      x86_64-specific, and right now, checking V=1 builds shows me
      that the flags is there anyway, although unused.
      Signed-off-by: NGlauber Costa <gcosta@redhat.com>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      d73a731a
    • G
      x86: use ignore macro instead of hash comment · 70f1bba4
      Glauber Costa 提交于
      In dwarf_64.h header, use the "ignore" macro the way
      i386 does.
      Signed-off-by: NGlauber Costa <gcosta@redhat.com>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      70f1bba4
    • G
      x86: use matching CFI_ENDPROC · 557d7d4e
      Glauber Costa 提交于
      The RING0_INT_FRAME macro defines a CFI_STARTPROC.
      So we should really be using CFI_ENDPROC after it.
      Signed-off-by: NGlauber Costa <gcosta@redhat.com>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      557d7d4e
    • L
      Merge branch 'upstream-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jgarzik/libata-dev · 4d727a78
      Linus Torvalds 提交于
      * 'upstream-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jgarzik/libata-dev:
        libata-acpi: don't call sleeping function from invalid context
        Added Targa Visionary 1000 IDE adapter to pata_sis.c
        libata-acpi: filter out DIPM enable
      4d727a78
    • D
      Fix reference counting race on log buffers · 49641f1a
      Dave Chinner 提交于
      When we release the iclog, we do an atomic_dec_and_lock to determine if
      we are the last reference and need to trigger update of log headers and
      writeout.  However, in xlog_state_get_iclog_space() we also need to
      check if we have the last reference count there.  If we do, we release
      the log buffer, otherwise we decrement the reference count.
      
      But the compare and decrement in xlog_state_get_iclog_space() is not
      atomic, so both places can see a reference count of 2 and neither will
      release the iclog.  That leads to a filesystem hang.
      
      Close the race by replacing the atomic_read() and atomic_dec() pair with
      atomic_add_unless() to ensure that they are executed atomically.
      Signed-off-by: NDave Chinner <david@fromorbit.com>
      Reviewed-by: NTim Shimmin <tes@sgi.com>
      Tested-by: NEric Sandeen <sandeen@sandeen.net>
      Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      49641f1a
    • I
      x86: fix savesegment() bug causing crashes on 64-bit · d9fc3fd3
      Ingo Molnar 提交于
      i spent a fair amount of time chasing a 64-bit bootup crash that manifested
      itself as bootup segfaults:
      
        S10network[1825]: segfault at 7f3e2b5d16b8 ip 00000031108748c9 sp 00007fffb9c14c70 error 4 in libc-2.7.so[3110800000+14d000]
      
      eventually causing init to die and panic the system:
      
        Kernel panic - not syncing: Attempted to kill init!
        Pid: 1, comm: init Not tainted 2.6.26-rc9-tip #13878
      
      after a maratonic bisection session, the bad commit turned out to be:
      
      | b7675791859075418199c7af86a116ea34eaf5bd is first bad commit
      | commit b7675791859075418199c7af86a116ea34eaf5bd
      | Author: Jeremy Fitzhardinge <jeremy@goop.org>
      | Date:   Wed Jun 25 00:19:00 2008 -0400
      |
      |     x86: remove open-coded save/load segment operations
      |
      |     This removes a pile of buggy open-coded implementations of savesegment
      |     and loadsegment.
      
      after some more bisection of this patch itself, it turns out that what
      makes the difference are the savesegment() changes to __switch_to().
      
      Taking a look at this portion of arch/x86/kernel/process_64.o revealed
      this crutial difference:
      
      | good:    99c:       8c e0                   mov    %fs,%eax
      |          99e:       89 45 cc                mov    %eax,-0x34(%rbp)
      |
      | bad:     99c:       8c 65 cc                mov    %fs,-0x34(%rbp)
      
      which is due to:
      
      |                 unsigned fsindex;
      | -               asm volatile("movl %%fs,%0" : "=r" (fsindex));
      | +               savesegment(fs, fsindex);
      
      savesegment() is implemented as:
      
       #define savesegment(seg, value)                                \
                asm("mov %%" #seg ",%0":"=rm" (value) : : "memory")
      
      note the "m" modifier - it allows GCC to generate the segment move
      into a memory operand as well.
      
      But regarding segment operands there's a subtle detail in the x86
      instruction set: the above 16-bit moves are zero-extend, but only
      if it goes to a register.
      
      If it goes to a memory operand, -0x34(%rbp) in the above case, there's
      no zero-extend to 32-bit and the instruction will only save 16 bits
      instead of the intended 32-bit.
      
      The other 16 bits is random data - which can cause problems when that
      value is used later on.
      
      The solution is to only allow segment operands to go to registers.
      This fix allows my test-system to boot up without crashing.
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      d9fc3fd3
  2. 11 7月, 2008 19 次提交