1. 18 1月, 2013 3 次提交
    • P
      usb: dwc3: gadget: fix missed isoc · 7efea86c
      Pratyush Anand 提交于
      There are two reasons to generate missed isoc.
      
      1. when the host does not poll for all the data.
      2. because of application-side delays that prevent all the data from
      being transferred in programmed microframe.
      
      Current code was able to handle first case only.  This patch handles
      scenario 2 as well.Scenario 2 sometime may occur with complex gadget
      application, however it can be easily reproduced for testing purpose as
      follows:
      
      a. use isoc binterval as 1 in f_sourcesink.
      b. use pattern=0
      c. introduce a delay of 150us deliberately in source_sink_complete, so
      that after few frames it lands into scenario 2.
      d. now run testusb 16 (isoc in  test). You will notice that if this
      patch is not applied then isoc transfer is not able to recover after
      first missed.
      
      Current patch's approach is as under:
      
      If missed isoc occurs and there is no request queued then issue END
      TRANSFER, so that core generates next xfernotready and we will issue a
      fresh START TRANSFER.
      If there are still queued request then wait, do not issue either END or
      UPDATE TRANSFER, just attach next request in request_list during giveback.
      If any future queued request is successfully transferred then we will issue
      UPDATE TRANSFER for all request in the request_list.
      
      Cc: <stable@vger.kernel.org> # v3.6 v3.7 v3.8
      Signed-off-by: NPratyush Anand <pratyush.anand@st.com>
      Signed-off-by: NFelipe Balbi <balbi@ti.com>
      7efea86c
    • F
      usb: dwc3: debugfs: convert our regdump to use regsets · d7668024
      Felipe Balbi 提交于
      regset is a generic implementation of regdump
      utility through debugfs.
      Signed-off-by: NFelipe Balbi <balbi@ti.com>
      d7668024
    • F
      usb: dwc3: decrease event buffer size · 5da93478
      Felipe Balbi 提交于
      Currently we're allocating an entire page to
      serve as our event buffer. Provided our events
      are 4 bytes long, it's very unlikely we will
      even trigger 1k events at once.
      
      Even in the worst case scenario where every
      endpoint triggers one event and we still have
      a couple of error events, that would still
      be less than 40 events.
      
      In order to cope with future versions of the
      IP which could (or could not) increase the
      amount of possible events to trigger
      simultaneously, we're using an arbitrary size
      of 64 events for our event buffer.
      
      We're saving 3840 bytes by doing so.
      Signed-off-by: NFelipe Balbi <balbi@ti.com>
      5da93478
  2. 31 10月, 2012 1 次提交
  3. 11 9月, 2012 1 次提交
  4. 03 8月, 2012 1 次提交
  5. 25 6月, 2012 1 次提交
  6. 06 6月, 2012 1 次提交
  7. 04 6月, 2012 4 次提交
  8. 04 5月, 2012 2 次提交
  9. 02 5月, 2012 3 次提交
  10. 30 4月, 2012 1 次提交
  11. 24 4月, 2012 1 次提交
  12. 11 4月, 2012 1 次提交
  13. 02 3月, 2012 2 次提交
  14. 28 2月, 2012 1 次提交
    • F
      usb: dwc3: gadget: use generic map/unmap routines · 0fc9a1be
      Felipe Balbi 提交于
      those routines have everything we need to map/unmap
      USB requests and it's better to use them.
      
      In order to achieve that, we had to add a simple
      change on how we allocate and use our setup buffer;
      we cannot allocate it from coherent anymore otherwise
      the generic map/unmap routines won't be able to easily
      know that the GetStatus request already has a DMA
      address.
      Signed-off-by: NFelipe Balbi <balbi@ti.com>
      0fc9a1be
  15. 13 2月, 2012 1 次提交
    • F
      usb: dwc3: convert TRBs into bitshifts · f6bafc6a
      Felipe Balbi 提交于
      this will get rid of a useless memcpy on
      IRQ handling, thus improving driver performance.
      
      Tested with OMAP5430 running g_mass_storage on
      SuperSpeed and HighSpeed.
      
      Note that we are removing the little endian access
      of the TRB and all accesses will be in System endianness,
      if there happens to be a system in BE, bit 12 of GSBUSCFG0
      should be set so that HW does byte invariant BE accesses
      when fetching TRBs.
      Signed-off-by: NFelipe Balbi <balbi@ti.com>
      f6bafc6a
  16. 10 2月, 2012 1 次提交
    • G
      usb: dwc3: ep0: fix SetFeature(TEST) · 3b637367
      Gerard Cauvy 提交于
      When host requests us to enter a test mode,
      we cannot directly enter the test mode before
      Status Phase is completed, otherwise the core
      will never be able to deliver the Status ZLP
      to host, because it has already entered the
      requested Test Mode.
      
      In order to fix the error, we move the actual
      start of Test Mode right after we receive
      Transfer Complete event of the status phase.
      Signed-off-by: NGerard Cauvy <g-cauvy1@ti.com>
      Signed-off-by: NFelipe Balbi <balbi@ti.com>
      3b637367
  17. 06 2月, 2012 3 次提交
  18. 12 12月, 2011 12 次提交