- 20 3月, 2014 40 次提交
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由 Lee Jones 提交于
When we write data to the Serial Flash chip we'll wait a predetermined period of time before giving up. During that period of time we poll the status register until completion. Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: NLee Jones <lee.jones@linaro.org> Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
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由 Lee Jones 提交于
When we write data to the FIFO the FSM Controller subsequently writes that data out to the Serial Flash chip. Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: NLee Jones <lee.jones@linaro.org> Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
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由 Lee Jones 提交于
When a read is issued by userspace the MTD framework calls back into the driver to conduct the actual command issue and data extraction. Here we provide the routines which do exactly that. Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: NLee Jones <lee.jones@linaro.org> Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
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由 Lee Jones 提交于
Most chips require a predefined set of FSM message sequences for read, write and erase operations. This patch provides a way to set them up, which it will do so if a chip specific initialisation routine isn't been provided. Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: NLee Jones <lee.jones@linaro.org> Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
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由 Lee Jones 提交于
In the FSM driver we handle chip differences by providing the possibility of calling back into a chip specific initialisation routine. In this patch we provide one for the N25Qxxx series, which endeavours to setup things like the read, write and erase sequences, as they differ from the default. We also configure 32bit support and the amount of dummy cycles to use. Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: NLee Jones <lee.jones@linaro.org> Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
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由 Lee Jones 提交于
The N25Qxxx Serial Flash devices required different sequence configurations depending on whether they're running in 24bit (3Byte) or 32bit (4Byte) mode. We provide those here. Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: NLee Jones <lee.jones@linaro.org> Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
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由 Lee Jones 提交于
Message sequences can vary depending on how many pads (lines) are required to address the chip (mode & dummy), how many data pads (lines) are required to write out to the chip which will determine speed amongst other things which are detailed by the SFDP specification. We are able to use multiple configurations for each chip, but they need to me matched to a device's capabilities. These configurations are listed in preference order - most preferred first. Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: NLee Jones <lee.jones@linaro.org> Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
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由 Lee Jones 提交于
The FSM Serial Flash Controller is driven by issuing a standard set of register writes we call a message sequence. This patch supplies a method to prepare the message sequence responsible for updating a chip's VCR. Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: NLee Jones <lee.jones@linaro.org> Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
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由 Lee Jones 提交于
Most Serial Flash chips support 24bit addressing as a default but more recent incarnations can support 32bit. Based on information provided though platform specific data and capabilities we can determine whether or not our current chip can. This patch provides a means to setup the FSM message sequence to put the chip into 32bit mode. Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: NLee Jones <lee.jones@linaro.org> Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
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由 Lee Jones 提交于
Based on information we can obtain though platform specific data and/or chip capabilities we are able to determine whether or not we can handle a SoC reset or not. To find out why this is important please read the comment provided in the patch. Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: NLee Jones <lee.jones@linaro.org> Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
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由 Lee Jones 提交于
Firstly we search for our preference read/write configuration based on a given chip's capabilities. Then we actually set up the message sequence accordingly. Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: NLee Jones <lee.jones@linaro.org> Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
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由 Lee Jones 提交于
The FSM Serial Flash Controller is driven by issuing a standard set of register writes we call a message sequence. This patch supplies a method to prepare the message sequence responsible for setting 32bit addressing mode on the Flash chip. Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: NLee Jones <lee.jones@linaro.org> Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
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由 Lee Jones 提交于
The FSM Serial Flash Controller is driven by issuing a standard set of register writes we call a message sequence. This patch supplies a method to prepare the message sequence responsible for erasing a single sector. Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: NLee Jones <lee.jones@linaro.org> Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
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由 Lee Jones 提交于
It's important for us to determine which device was used to boot from in order to make some correct decisions surrounding Power Management. On each of the platforms which support the FSM this is communicated via a set of mode pins held in the system configuration area. This patch determine the boot device and stores the result. Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: NLee Jones <lee.jones@linaro.org> Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
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由 Lee Jones 提交于
Cc: devicetree@vger.kernel.org Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: NLee Jones <lee.jones@linaro.org> Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
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由 Lee Jones 提交于
The FSM Serial Flash Controller is driven by issuing a standard set of register writes we call a message sequence. This patch supplies a method to prepare read/write FSM message sequence(s) based on chip capability and configuration. Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: NLee Jones <lee.jones@linaro.org> Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
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由 Lee Jones 提交于
Take some known parameters, namely size and number of sectors and use them to determine weather a device can support 32bit addressing or not. If it can, set the associated flash capability flag for latter use. Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: NLee Jones <lee.jones@linaro.org> Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
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由 Lee Jones 提交于
Here we provide a means to traverse though all supplied FSM message sequence configurations and pick one based on our chip's capabilities. The first one we match will be the preferred one, as they are presented in order of preference. Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: NLee Jones <lee.jones@linaro.org> Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
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由 Lee Jones 提交于
Using previously added infrastructure we can now extract a device's JEDEC ID, compare it to a list of known and supported devices and make assumptions based on known characteristics of a given chip. Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: NLee Jones <lee.jones@linaro.org> Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
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由 Lee Jones 提交于
Supply a lookup table of all the devices we intend to support. This table is used to store device information such as; a human readable device name, their JEDEC ID (plus the extended version), sector size and amount, a bit store of a device's capabilities, its maximum running frequency and possible use of a per-device configuration call-back. Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: NLee Jones <lee.jones@linaro.org> Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
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由 Lee Jones 提交于
JEDEC have helped to standardise a great deal of the commands which can be issued to a Serial Flash devices. Many of the Serial Flash Discoverable Parameters (SFDP) commands are generic across devices. This patch provides a shared point where these commands can be defined. Suggested-by: NMark Brown <broonie@kernel.org> Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: NLee Jones <lee.jones@linaro.org> Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
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由 Lee Jones 提交于
Once we start supporting devices it will be handy go detect them dynamically. This will be done using the chip's unique JEDEC ID. This patch allows us to extract a device's JEDEC ID using the a predefined FSM register write sequence. Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: NLee Jones <lee.jones@linaro.org> Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
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由 Lee Jones 提交于
When invoked the driver will attempt to read any available data from the FSM's data register. Any data collected from this FIFO would have originated from the flash chip. Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: NLee Jones <lee.jones@linaro.org> Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
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由 Lee Jones 提交于
The FSM hardware works by setting a predetermined sequence of register writes. Rather than open coding them inside each functional block we're going to define them in a series of formatted 'sequence structures'. This patch provides the framework which shall be used for every action. Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: NLee Jones <lee.jones@linaro.org> Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
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由 Lee Jones 提交于
This patch uses default values to initialise a connected flash chip. This includes; a device soft reset, setting of a safe working frequency, a switch into Fast Sequencing Mode, configuring of timing data and a purge of the FIFO. Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: NLee Jones <lee.jones@linaro.org> Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
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由 Lee Jones 提交于
Here we provide the FSM's register addresses, register bit names/offsets and some commands which will prove useful as we start bulk the FMS's driver out with functionality. Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: NLee Jones <lee.jones@linaro.org> Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
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由 Lee Jones 提交于
This is a new driver. It's used to communicate with a special type of optimised Serial Flash Controller called the FSM. The FSM uses a subset of the SPI protocol to communicate with supported NOR-Flash devices. Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: NLee Jones <lee.jones@linaro.org> Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
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由 Pekon Gupta 提交于
'is_elm_present' flag is not used anywhere. This check is implicitely taken care while selecting appropriate ecc-scheme via DT or board-file. Signed-off-by: NPekon Gupta <pekon@ti.com> Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
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由 Pekon Gupta 提交于
This patch - refactors GPMC configurations based on ecc-scheme - removed dependency on is_elm_present() flag, which is implicitely taken care by selecting appropriate ecc-scheme Signed-off-by: NPekon Gupta <pekon@ti.com> Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
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由 Pekon Gupta 提交于
Lots of if..then..else conditions in omap_enable_hwecc_bch() can be avoided if code is refactored based on ecc-scheme. Signed-off-by: NPekon Gupta <pekon@ti.com> Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
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由 Pekon Gupta 提交于
This patch - renames omap3_enable_hwecc_bch -> omap_enable_hwecc_bch to keep nomenclature independent of any device family. - using '__maybe_unused' instead of `ifdef based conditional compilation to suppress warning for un-used functions Signed-off-by: NPekon Gupta <pekon@ti.com> Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
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由 Pekon Gupta 提交于
merge omap3_calculate_ecc_bch8() into omap_calculate_ecc_bch() so that common callback can be used for both OMAP_ECC_BCH8_CODE_HW and OMAP_ECC_BCH8_CODE_HW_DETECTION_SW +---------------------+-------------------------------------------------------+ |ecc-scheme | nand_chip->calculate() after this patch | +---------------------+-------------------------------------------------------+ |HAM1_ECC | omap_calculate_ecc() | +---------------------+-------------------------------------------------------+ |BCH4_HW_DETECTION_SW | omap_calculate_ecc_bch() | |BCH4_HW | omap_calculate_ecc_bch() | |BCH8_HW_DETECTION_SW | omap3_calculate_ecc_bch8() -> omap_calculate_ecc_bch()| |BCH8_HW | omap_calculate_ecc_bch() | +---------------------+-------------------------------------------------------+ Tested-by: NStefan Roese <sr@denx.de> Signed-off-by: NPekon Gupta <pekon@ti.com> Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
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由 Pekon Gupta 提交于
merges omap3_calculate_ecc_bch4() into omap_calculate_ecc_bch() so that common callback can be used for both OMAP_ECC_BCH4_CODE_HW and OMAP_ECC_BCH4_CODE_HW_DETECTION_SW ecc-schemes +---------------------+-------------------------------------------------------+ |ecc-scheme | nand_chip->calculate() after this patch | +---------------------+-------------------------------------------------------+ |HAM1_ECC | omap_calculate_ecc() | +---------------------+-------------------------------------------------------+ |BCH4_HW_DETECTION_SW | omap3_calculate_ecc_bch4() -> omap_calculate_ecc_bch()| |BCH4_HW | omap_calculate_ecc_bch() | |BCH8_HW_DETECTION_SW | omap3_calculate_ecc_bch8() | |BCH8_HW | omap_calculate_ecc_bch() | +---------------------+-------------------------------------------------------+ Tested-by: NStefan Roese <sr@denx.de> Signed-off-by: NPekon Gupta <pekon@ti.com> Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
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由 Pekon Gupta 提交于
OMAP NAND driver supports multiple flavours of BCH4 and BCH8 ECC algorithms. +------+------------------------------------+---------------+---------------+ | Algo | ECC scheme |ECC calculation|Error detection| +------+------------------------------------+---------------+---------------+ | |OMAP_ECC_BCH4_CODE_HW_DETECTION_SW |H/W (GPMC) |S/W | | BCH4 |OMAP_ECC_BCH4_CODE_HW |H/W (GPMC) |H/W (ELM) | +------+------------------------------------+---------------+---------------+ | |OMAP_ECC_BCH8_CODE_HW_DETECTION_SW |H/W (GPMC) |S/W | | BCH8 |OMAP_ECC_BCH8_CODE_HW |H/W (GPMC) |H/W (ELM) | +------+------------------------------------+---------------+---------------+ This patch refactors omap_calculate_ecc_bch() so that - separate out ecc-scheme specific code so that common-code can be reused between different implementations of same ECC algorithm. - new ecc-schemes can be added with ease in future. Tested-by: NStefan Roese <sr@denx.de> Signed-off-by: NPekon Gupta <pekon@ti.com> Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
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由 Pekon Gupta 提交于
rename omap3_calculate_ecc_bch -> omap_calculate_ecc_bch to keep nomenclature independent of any device family. Tested-by: NStefan Roese <sr@denx.de> Signed-off-by: NPekon Gupta <pekon@ti.com> Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
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由 Pekon Gupta 提交于
This patch updates following checks when bit-flips are detected by ELM: - Do not evaluate bit-flips when un-correctable bit-flips is reported by ELM, because as per [1] when ELM reports an un-correctable bit-flips, 'number of error' field in its ELM_LOCATION_STATUS register is also invalid. - Return with error-code '-EBADMSG' on detection of un-correctable bit-flip. - Return with error-code '-EBADMSG' when bit-flips position is outside current Sector and OOB area. [1] ELM IP spec Table-25 ELM_LOCATION_STATUS Register. ELM_LOCATION_STATUS[8] = ECC_CORRECTABLE: Error location process exit status 0x0: ECC error location process failed. Number of errors and error locations are invalid. 0x1: all errors were successfully located. Number of errors and error locations are valid. Tested-by: NStefan Roese <sr@denx.de> Signed-off-by: NPekon Gupta <pekon@ti.com> Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
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由 Pekon Gupta 提交于
Current omap_elm_correct_data() code is not scalable for future ecc-schemes due to presence of tweaks and hard-coded macros for BCH4_ECC and BCH8_ECC ecc-schemes at multiple places. This patch: - replaces 'ecc_opt' with '(info->nand.ecc.strength == BCH8_MAX_ERROR) used to differentiate between BCH8_HW and BCH4_SW - replaces macros (defining magic number for specific ecc-scheme) with generic variables - removes dependency on macros defined in elm.h (like BCHx_ECC_OOB_BYTES) Tested-by: NStefan Roese <sr@denx.de> Signed-off-by: NPekon Gupta <pekon@ti.com> Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
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由 Pekon Gupta 提交于
mtd: nand: omap: ecc.correct: omap_elm_correct_data: fix erased-page detection for BCHx_HW ECC schemes As erased-pages do not have ECC stored in their OOB area, so they need to be seperated out from programmed-pages, before doing BCH ECC correction. In current implementation of omap_elm_correct_data() which does ECC correction for BCHx ECC schemes, this erased-pages are detected based on specific marker byte (reserved as 0x00) in ecc-layout. However, this approach has some limitation like; 1) All ecc-scheme layouts do not have such Reserved byte marker to differentiate between erased-page v/s programmed-page. Thus this is a customized solution. 2) Reserved marker byte can itself be subjected to bit-flips causing erased-page to be misunderstood as programmed-page. This patch removes dependency on any marker byte in ecc-layout, instead it compares calc_ecc[] with pattern of ECC-of-all(0xff). This implicitely means that both 'data + oob == all(0xff). Signed-off-by: NPekon Gupta <pekon@ti.com> Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
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由 Pekon Gupta 提交于
mtd: nand: omap: ecc.correct: omap_elm_correct_data: rename ambiguous variable 'eccsize' and 'ecc_vector_size' renaming following variables as they cause confusion due to resemblence to another similar field in 'struct nand_ecc_ctrl' (nand_chip->ecc.size). renaming: ecc_vector_size --> ecc->bytes (info->nand.ecc.bytes) renaming: eccsize --> actual_eccbytes (info->nand.ecc.bytes - 1) for BCH4 and BCH8 Tested-by: NStefan Roese <sr@denx.de> Signed-off-by: NPekon Gupta <pekon@ti.com> Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
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由 Pekon Gupta 提交于
Information of currently selected ECC scheme 'enum omap_ecc ecc_opt' should available outside platform-data, so that single nand_chip->ecc callback can support multiple ecc-scheme configurations. Tested-by: NStefan Roese <sr@denx.de> Signed-off-by: NPekon Gupta <pekon@ti.com> Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
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