1. 29 12月, 2011 2 次提交
    • S
      drm/exynos: added hdmi display support · d8408326
      Seung-Woo Kim 提交于
      This patch is hdmi display support for exynos drm driver.
      
      There is already v4l2 based exynos hdmi driver in drivers/media/video/s5p-tv
      and some low level code is already in s5p-tv and even headers for register
      define are almost same. but in this patch, we decide not to consider separated
      common code with s5p-tv.
      
      Exynos HDMI is composed of 5 blocks, mixer, vp, hdmi, hdmiphy and ddc.
      
      1. mixer. The piece of hardware responsible for mixing and blending multiple
      data inputs before passing it to an output device.  The mixer is capable of
      handling up to three image layers. One is the output of VP.  Other two are
      images in RGB format.  The blending factor, and layers' priority are controlled
      by mixer's registers. The output is passed to HDMI.
      
      2. vp (video processor). It is used for processing of NV12/NV21 data.  An image
      stored in RAM is accessed by DMA. The output in YCbCr444 format is send to
      mixer.
      
      3. hdmi. The piece of HW responsible for generation of HDMI packets. It takes
      pixel data from mixer and transforms it into data frames. The output is send
      to HDMIPHY interface.
      
      4. hdmiphy. Physical interface for HDMI. Its duties are sending HDMI packets to
      HDMI connector. Basically, it contains a PLL that produces source clock for
      mixer, vp and hdmi.
      
      5. ddc (display data channel). It is dedicated i2c channel to exchange display
      information as edid with display monitor.
      
      With plane support, exynos hdmi driver fully supports two mixer layes and vp
      layer. Also vp layer supports multi buffer plane pixel formats having non
      contigus memory spaces.
      
      In exynos drm driver, common drm_hdmi driver to interface with drm framework
      has opertion pointers for mixer and hdmi. this drm_hdmi driver is registered as
      sub driver of exynos_drm. hdmi has hdmiphy and ddc i2c clients and controls
      them. mixer controls all overlay layers in both mixer and vp.
      
      Vblank interrupts for hdmi are handled by mixer internally because drm
      framework cannot support multiple irq id. And pipe number is used to check
      which display device irq happens.
      
      History
      v2: this version
       - drm plane feature support to handle overlay layers.
       - multi buffer plane pixel format support for vp layer.
       - vp layer support
      
      RFCv1: original
       - at https://lkml.org/lkml/2011/11/4/164Signed-off-by: NSeung-Woo Kim <sw0312.kim@samsung.com>
      Signed-off-by: NInki Dae <inki.dae@samsung.com>
      Signed-off-by: NJoonyoung Shim <jy0922.shim@samsung.com>
      Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com>
      d8408326
    • S
      drm: Add multi buffer plane pixel formats · 83052d4d
      Seung-Woo Kim 提交于
      Multi buffer plane pixel format has seperated memory spaces for each
      plane. For example, NV12M has Y plane and CbCr plane and these are in
      non contiguous memory region. Compared with NV12, NV12M's memory shape
      is like following.
      NV12  : ______(Y)(CbCr)_______
      NV12M : __(Y)_ ..... _(CbCr)__
      Signed-off-by: NSeung-Woo Kim <sw0312.kim@samsung.com>
      Signed-off-by: NInki Dae <inki.dae@samsung.com>
      Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com>
      83052d4d
  2. 22 12月, 2011 6 次提交
  3. 21 12月, 2011 2 次提交
  4. 20 12月, 2011 5 次提交
  5. 14 12月, 2011 1 次提交
  6. 06 12月, 2011 19 次提交
  7. 02 12月, 2011 1 次提交
  8. 01 12月, 2011 1 次提交
    • V
      drm: Redefine pixel formats · 04b3924d
      Ville Syrjälä 提交于
      Name the formats as DRM_FORMAT_X instead of DRM_FOURCC_X. Use consistent
      names, especially for the RGB formats. Component order and byte order are
      now strictly specified for each format.
      
      The RGB format naming follows a convention where the components names
      and sizes are listed from left to right, matching the order within a
      single pixel from most significant bit to least significant bit.
      
      The YUV format names vary more. For the 4:2:2 packed formats and 2
      plane formats use the fourcc. For the three plane formats the
      name includes the plane order and subsampling information using the
      standard subsampling notation. Some of those also happen to match
      the official fourcc definition.
      
      The fourccs for for all the RGB formats and some of the YUV formats
      I invented myself. The idea was that looking at just the fourcc you
      get some idea what the format is about without having to decode it
      using some external reference.
      Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com>
      Signed-off-by: NDave Airlie <airlied@redhat.com>
      04b3924d
  9. 30 11月, 2011 1 次提交
  10. 23 11月, 2011 1 次提交
  11. 20 11月, 2011 1 次提交
    • M
      drm/radeon/kms: add a CS ioctl flag not to rewrite tiling flags in the CS · e70f224c
      Marek Olšák 提交于
      This adds a new optional chunk to the CS ioctl that specifies optional flags
      to the CS parser. Why this is useful is explained below. Note that some regs
      no longer need the NOP relocation packet if this feature is enabled.
      Tested on r300g and r600g with this flag disabled and enabled.
      
      Assume there are two contexts sharing the same mipmapped tiled texture.
      One context wants to render into the first mipmap and the other one
      wants to render into the last mipmap. As you probably know, the hardware
      has a MACRO_SWITCH feature, which turns off macro tiling for small mipmaps,
      but that only applies to samplers.
      (at least on r300-r500, though later hardware likely behaves the same)
      
      So we want to just re-set the tiling flags before rendering (writing
      packets), right? ... No. The contexts run in parallel, so they may
      set the tiling flags simultaneously and then fire their command streams
      also simultaneously. The last one setting the flags wins, the other one
      loses.
      
      Another problem is when one context wants to render into the first and
      the last mipmap in one CS. Impossible. It must flush before changing
      tiling flags and do the rendering into the smaller mipmaps in another CS.
      
      Yet another problem is that writing copy_blit in userspace would be a mess
      involving re-setting tiling flags to please the kernel, and causing races
      with other contexts at the same time.
      
      The only way out of this is to send tiling flags with each CS, ideally
      with each relocation. But we already do that through the registers.
      So let's just use what we have in the registers.
      Signed-off-by: NMarek Olšák <maraeo@gmail.com>
      Signed-off-by: NDave Airlie <airlied@redhat.com>
      e70f224c