- 24 4月, 2010 1 次提交
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由 Santosh Shilimkar 提交于
This patch fixes the base address of CONTROL register on OMAP4430SDP. The control base is used by peripherals like MMC1 for PBIAS configuration. Signed-off-by: NSantosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: NKishore Kadiyala <kishore.kadiyala@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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- 24 2月, 2010 1 次提交
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由 Maulik Mankad 提交于
This patch adds support for Mentor USB to 4430 SDP board file. It also defines the base address for HS USB OTG controller in OMAP4. Also updates platform specfic structure with base address and IRQ details. Signed-off-by: NMaulik Mankad <x0082077@ti.com> Cc: Tony Lindgren <tony@atomide.com> Cc: Felipe Balbi <felipe.balbi@nokia.com> Cc: David Brownell <david-b@pacbell.net> Cc: Greg Kroah-Hartman <gregkh@suse.de> Cc: Sergei Shtylyov <sshtylyov@ru.mvista.com> Cc: Olof Johansson <olof@lixom.net> Signed-off-by: NTony Lindgren <tony@atomide.com>
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- 16 2月, 2010 2 次提交
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由 Santosh Shilimkar 提交于
This patch adds L2 Cache support for OMAP4. External L2 cache is used in OMAP4 CC: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: NSantosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: NTony Lindgren <tony@atomide.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Jorge Eduardo Candelaria 提交于
Define McPDM physical and L3 base address for OMAP4 Signed-off-by: NJorge Eduardo Candelaria <x0107209@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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- 12 12月, 2009 1 次提交
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由 Rajendra Nayak 提交于
This patch fixes the PRM and CM base addresses and adds a new CM2 base address for OMAP4 Signed-off-by: NRajendra Nayak <rnayak@ti.com> Signed-off-by: NPaul Walmsley <paul@pwsan.com> Cc: Benoit Cousson <b-cousson@ti.com>
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- 23 11月, 2009 1 次提交
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由 C A Subramaniam 提交于
This patch adds resource information of mailbox driver for OMAP4 mailbox module. Register base address also added Signed-off-by: NC A Subramaniam <subramaniam.ca@ti.com> Signed-off-by: NRamesh Gupta G <grgupta@ti.com> Acked-by: NHiroshi DOYU <Hiroshi.DOYU@nokia.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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- 21 10月, 2009 1 次提交
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由 Tony Lindgren 提交于
Move the remaining headers under plat-omap/include/mach to plat-omap/include/plat. Also search and replace the files using these headers to include using the right path. This was done with: #!/bin/bash mach_dir_old="arch/arm/plat-omap/include/mach" plat_dir_new="arch/arm/plat-omap/include/plat" headers=$(cd $mach_dir_old && ls *.h) omap_dirs="arch/arm/*omap*/ \ drivers/video/omap \ sound/soc/omap" other_files="drivers/leds/leds-ams-delta.c \ drivers/mfd/menelaus.c \ drivers/mfd/twl4030-core.c \ drivers/mtd/nand/ams-delta.c" for header in $headers; do old="#include <mach\/$header" new="#include <plat\/$header" for dir in $omap_dirs; do find $dir -type f -name \*.[chS] | \ xargs sed -i "s/$old/$new/" done find drivers/ -type f -name \*omap*.[chS] | \ xargs sed -i "s/$old/$new/" for file in $other_files; do sed -i "s/$old/$new/" $file done done for header in $(ls $mach_dir_old/*.h); do git mv $header $plat_dir_new/ done Signed-off-by: NTony Lindgren <tony@atomide.com>
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- 20 10月, 2009 2 次提交
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由 Santosh Shilimkar 提交于
This patch adds few necessary peripherals for OMAP4. Signed-off-by: NSantosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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由 Tony Lindgren 提交于
Use ioremap for omap4 L4 code Signed-off-by: NSantosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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- 29 8月, 2009 1 次提交
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由 Tony Lindgren 提交于
Search and replace OMAP_IO_ADDRESS with OMAP1_IO_ADDRESS and OMAP2_IO_ADDRESS, and convert omap_read/write into a functions instead of a macros. Also rename OMAP_MPUIO_VBASE to OMAP1_MPUIO_VBASE. In the long run, most code should use ioremap + __raw_read/write instead. Signed-off-by: NTony Lindgren <tony@atomide.com>
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- 29 5月, 2009 1 次提交
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由 Santosh Shilimkar 提交于
This patch adds the support for OMAP4. The platform and machine specific headers and sources updated for OMAP4430 SDP platform. OMAP4430 is Texas Instrument's SOC based on ARM Cortex-A9 SMP architecture. It's a dual core SOC with GIC used for interrupt handling and SCU for cache coherency. Signed-off-by: NSantosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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