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  1. 15 8月, 2015 20 次提交
  3. 14 8月, 2015 20 次提交
    • P
      usb: chipidea: add tx/rx burst size configuration interface · 96625ead
      由 Peter Chen 提交于 
      The user can adjust it through dts or platform data
Signed-off-by: NPeter Chen <peter.chen@freescale.com>
      96625ead
    • P
      Doc: usb: ci-hdrc-usb2: add tx(rx)-burst-config-dword for binding doc · bd6e9d11
      由 Peter Chen 提交于 
      It is used to override the default setting for burst size, changing
burst size takes effect only when the SBUSCFG.AHBBRST = 0.
Signed-off-by: NPeter Chen <peter.chen@freescale.com>
      bd6e9d11
    • P
      usb: chipidea: usbmisc_imx: add non-burst setting for imx6 · ed6e5eb5
      由 Peter Chen 提交于 
      With this setting and AHBBRST at SBUSCFG as "Incremental burst of
unspecified length", each non-burst size can be taken as single
transfer. It is benefit for non-burst size transfer.
Signed-off-by: NPeter Chen <peter.chen@freescale.com>
      ed6e5eb5
    • P
      usb: chipidea: add ahb burst configuration interface · 65668718
      由 Peter Chen 提交于 
      The users can change it through dts or platform data if they
want to change the default value.
Signed-off-by: NPeter Chen <peter.chen@freescale.com>
      65668718
    • P
      Doc: usb: ci-hdrc-usb2: add ahb-burst-config for binding doc · c6fba7b7
      由 Peter Chen 提交于 
      It is used to change ahb burst configuration for platforms, it is
vendor specific.
Signed-off-by: NPeter Chen <peter.chen@freescale.com>
      c6fba7b7
    • P
      usb: chipidea: imx: add stream mode enable for device mode at imx6sl/imx6sx · 0ef877a4
      由 Peter Chen 提交于 
      Stream mode enable is known for better performance, this stream mode
enable patch has been passed with stress tests at device mode for
imx6sl and imx6sx, and no issue is found.
Signed-off-by: NPeter Chen <peter.chen@freescale.com>
      0ef877a4
    • P
      usb: chipidea: define stream mode disable for both roles · 8022d3d5
      由 Peter Chen 提交于 
      The system bus and chipidea IP have different limitations for
both host and device mode.
For example, with below errata, we need to enable SDIS(Stream Disable
Mode) at host mode. But we don't want it for device mode at the
same system.

TAR 9000378958
Title: Non-Double Word Aligned Buffer Address Sometimes Causes Host to
Hang on OUT Retry
Impacted Configuration: Host mode, all transfer types
Description:
The host core operating in streaming mode may under run while sending
the data packet of an OUT transaction. This under run can occur if
there are unexpected system delays in fetching the remaining packet
data from memory. The host forces a bad CRC on the packet, the device
detects the error and discards the packet. The host then retries a Bulk,
Interrupt, or Control transfer if an under run occurs according to the
USB specification. During simulations, it was found that the host does
not issue the retry of the failed bulk OUT. It does not issue any other
transactions except SOF packets that have incorrect frame numbers.

The second failure mode occurs if the under run occurs on an ISO OUT
transaction and the next ISO transaction is a zero byte packet. The host
does not issue any transactions (including SOFs). The device detects a
Suspend condition, reverts to full speed, and waits for resume signaling.

A third failure mode occurs when the host under runs on an ISO OUT and
the next ISO in the schedule is an ISO OUT with two max packets of 1024
bytes each. The host should issue MDATA for the first OUT followed by
DATA1 for the second. However, it drops the MDATA transaction, and
issues the DATA1 transaction.

The system impact of this bug is the same regardless of the failure mode
observed. The host core hangs, the ehci_ctrl state machine waits for the
protocol engine to send the completion status for the corrupted
transaction, which never occurs. No indication is sent to the host
controller driver, no register bits change and no interrupts occur.
Eventually the requesting application times out.

Detailed internal behavior:
The EHCI control state machine (ehci_ctrl) in the DMA block is responsible
for parsing the schedules and initiating all transactions. The ehci_ctrl
state machine passes the transaction details to the protocol block by
writing the transaction information in to the TxFIFO. It then asserts
the pe_hst_run_pkt signal to inform the host protocol state machine
(pe_hst_state) that there is a packet in the TxFIFO.
A tag of 0x0 indicates a start of packet with the data providing the
following information:

35:32 Tag
31:30 Reserved
29:23 Endpoint (lowest 4 bits)
22:16 Address
15:10 Reserved
9:8 Endpoint speed
7:6 Endpoint type
5:6 Data Toggle
3:0 PID
The pe_hst_state reads the packet information and constructs the packet
and issues it to the PHY interface.
The ehci_ctrl state machine writes the start transaction information in
to the TxFIFO as 0x03002910c for the OUT packet that had the under run
error. However, it writes 0xC3002910C for the retry of the Out
transaction, which is incorrect.
The pe_hst_state enters a bus timeout state after sending the bad CRC
for the packet that under ran. It then purges any data that was back
filled in to the TxFIFO for the packet that under ran. The pe_hst_state
machine stops purging the TxFIFO when it is empty or if it reads a
location that has a tag of 0x0, indicating a start of packet command.

The pe_hst_state reads 0xC3002910C and discards it as it does not decode
to a start of packet command. It continues to purge the OUT data that
has been pre-buffered for the OUT retry . The pe_hst_state detects the
hst_packet_run signal and attempts to read the PID and address
information from the TxFIFO. This location has packet data and so does
not decode to a valid PID and so falls through to the PE_HST_SOF_LOAD
state where the frame_num_counter is updated. The frame_num_counter
is updated with the data in the TxFIFO. In this case, the data is
incorrect as the ehci_ctrl state machine did not initiate the load.
The hst_pe_state machine detects the SOF request signal and sends an
SOF with the bad frame number. Meanwhile, the ehci_ctrl state machine
waits indefinitely in the run_pkt state waiting for the completion
status from pe_hst_state machine, which will never happen.

The ISO failure case is similar except that there is no retry for ISO.
The ehci_ctrl state machine moves to the next transfer in the periodic
schedule. If the under run occurs on the last entry of the periodic
list then it moves to the Async schedule.

In the case of ISO OUT simulations, the next ISO is a zero byte OUT
and again the start of packet command gets corrupted. The TxFIFO is
empty when the hst_pe_state attempts to read the Address and PID
information as the transaction is a zero byte packet. This results
in the hst_pe_state machine staying in the GET_PID state, which means
that it does not issue any transactions (including SOFs). The device
detects a Suspend condition and reverts to full speed mode and waits
for a Resume or Reset signal.

The EHCI specification allows a Non-DoubleWord (32 bits) offset to
be used as a current offset for Buffer Pointer Page 0 of the qTD.
In Non-DoubleWord aligned cases, the core reads the packet data
from the AHB memory, performs the alignment operation before writing
it in to the TxFIFO as a 32 bit data word. An End Of Packet tag (EOP)
is written to the TxFIFO after all the packet data has been written
in to the TxFIFO. The alignment function is reset to Idle by the EOP
tag. The corruption of the start of packet command arises because the
packet buffer for the OUT transaction that under ran is not aligned
to a DoubleWord, and hence no EOP tag is written to the TxFIFO. The
alignment function is still active when the start packet information
is written in to the TxFIFO for the retry of the bulk packet or for
the next transaction in the case of an under run on an ISO. This
results in the corruption of the start tag and the transaction
information.

Click for waveform showing the command 0x 0000300291 being written in
to the TX FIFO for the Out that under ran.
Click for waveform showing the command 0xC3002910C written to the
TxFIFO instead of 0x 0000300291
Versions affected: Versions 2.10a and previous versions
How discovered: Customer simulation

Workaround:
1- The EHCI specification allows a non-DoubleWord offset to be used
as a current offset for Buffer Pointer Page 0 of the qTD. However,
if a DoubleWord offset is used then this issue does not arise.
2- Use non streaming mode to eliminate under runs.

Resolution:
The fix involves changes to the traffic state machine in the
vusb_hs_dma_traf block. The ehci_ctrl state machine updates the context
information by encoding the transaction results on the
hst_op_context_update signals at the end of a transaction. The signal
hst_op_context_update is added to the traffic state machine, and the
tx_fifo_under_ran_r signal is generated if the transaction results in
an under run error. Click for waveform

The traffic state machine then traverses to the do_eop states if the
tx_fifo_under_ran error is asserted. Thus an EOP tag is written in to
the TxFIFO as shown in this waveform .

The EOP tag resets the align state machine to the Idle state ensuring
that the next command written by the echi_ctrl state machine does not
get corrupted.

File(s) modified:
RTL code fixed: …..
Method of reproducing: This failure cannot be reproduced in the current
test bench.
Date Found: March 2010
Date Fixed: June 2010
Update information:
Added the RTL code fix
Signed-off-by: NPeter Chen <peter.chen@freescale.com>
      8022d3d5
    • P
      usb: chipidea: udc: zero-length packet is only needed for TX · a4da4f12
      由 Peter Chen 提交于 
      The zero-length packet is the sendor tells the receiver that there
is no more data, so it is only needed at the TX side.
Signed-off-by: NPeter Chen <peter.chen@freescale.com>
      a4da4f12
    • P
      usb: chipidea: host: override hcd reset API · 11a27098
      由 Peter Chen 提交于 
      The system configuration API should be called before the controller
run, otherwise, undefined results may occur. So, we override hcd
reset API, and add system configuration API after controller reset.

Cc: Li Jun <peter.chen@freescale.com>
Cc: Alan Stern <stern@rowland.harvard.edu>
Acked-by: NAlan Stern <stern@rowland.harvard.edu>
Signed-off-by: NPeter Chen <peter.chen@freescale.com>
      11a27098
    • T
      usb: chipidea: imx: properly check for usbmisc · ef12da91
      由 Tomeu Vizoso 提交于 
      If usbmisc hasn't probed yet, defer the probe.

It's not enough to check if the platform device for the OF node of the
usbmisc has been registered, but it also needs to have been probed
already before we can call imx_usbmisc_init().

This can happen if the order in which devices are probed change due to
async probing or on-demand probing of dependencies.
Signed-off-by: NTomeu Vizoso <tomeu.vizoso@collabora.com>
      ef12da91
    • L
      usb: chipidea: debug: add runtime pm for register access · bc249379
      由 Li Jun 提交于 
      Add runtime pm operations for registers access to avoid system hang.
Signed-off-by: NLi Jun <jun.li@freescale.com>
      bc249379
    • N
      usb:chipidea:Make the function hw_alloc_repmap have a return type of void · 158ec071
      由 Nicholas Krause 提交于 
      This makes the function hw_alloc_repmap be declared to have a return
type of void now due to this particular function never returning
a error code to its caller due to this function always running
successfully to completion nor it's caller putting the return
value into a variable in order to check if a error code is passed
from the function hw_alloc_repmap when calling this function.
Signed-off-by: NNicholas Krause <xerofoify@gmail.com>
      158ec071
    • P
      usb: chipidea: host: delete the redundancy ci_hdrc struct · 1311d6e3
      由 Peter Chen 提交于 
      The struct ci_hdrc is the drvdata for hcd device, so we don't
need to introduce extra ci_hdrc structure for ehci.
Signed-off-by: NPeter Chen <peter.chen@freescale.com>
      1311d6e3
    • P
      usb: chipidea: introduce ITC tuning interface · df96ed8d
      由 Peter Chen 提交于 
      ITC (Interrupt Threshold Control) is used to set the maximum rate at which
the host/device controller will issue interrupts. The default value is 8 (1ms)
for it. EHCI core will modify it to 1, but device mode keeps it as default
value.

In some use cases like Android ADB, it only has one usb request for each
direction, and maximum payload data is only 4KB, so the speed is 4MB/s
at most, it needs controller to trigger interrupt as fast as possible
to increase the speed. The USB performance will be better if the interrupt
can be triggered faster.

Reduce ITC value is benefit for USB performance, but the interrupt number
is increased at the same time, it may increase cpu utilization too.
Most of use case cares about performance, but some may care about
cpu utilization, so, we leave a platform interface for user.
We set ITC as 1 (1 micro-frame) as default value which is aligned
with ehci core default value.
Signed-off-by: NPeter Chen <peter.chen@freescale.com>
      df96ed8d
    • P
      Doc: usb: ci-hdrc-usb2: add itc-setting at binding doc · 1bd57127
      由 Peter Chen 提交于 
      It is used to configure the ITC (in register USBCMD) value
for kinds of applications.
Signed-off-by: NPeter Chen <peter.chen@freescale.com>
      1bd57127
    • P
      usb: chipidea: introduce ci_platform_configure · bf9c85e7
      由 Peter Chen 提交于 
      It is used to configure controller parameters according to
platform data, like speed, stream mode, etc, both host and
device's initialization need it, most of code are the
same for both roles, with this new interface, it can reduce
the duplicated code and be easy to maintain in future.
Signed-off-by: NPeter Chen <peter.chen@freescale.com>
      bf9c85e7
    • P
      usb: chipidea: otg_fsm: delete the duplicated reset controller operation · 9d2effea
      由 Peter Chen 提交于 
      At host_stop, it will call usb_remove_hcd, and reset controller later.
Signed-off-by: NPeter Chen <peter.chen@freescale.com>
      9d2effea
    • P
      usb: chipidea: udc: add USB_DEVICE_A_HNP_SUPPORT request support · 3520d462
      由 Peter Chen 提交于 
      We can support USB OTG 1.3 USB_DEVICE_A_HNP_SUPPORT request when
the driver supports OTG FSM mode.
Signed-off-by: NPeter Chen <peter.chen@freescale.com>
      3520d462
    • P
      usb: chipidea: imx: enable CI_HDRC_SET_NON_ZERO_TTHA · e765bfb7
      由 Peter Chen 提交于 
      For i.mx platform, set ttctrl.ttha with non-zero value only affects
sitd, and ehci core makes sure the schedule is not full when accepts
new request, so it will not occur the transaction which will acorss
the SoF.
Signed-off-by: NPeter Chen <peter.chen@freescale.com>
      e765bfb7
    • P
      usb: chipidea: add ttctrl.ttha control interface · 28362673
      由 Peter Chen 提交于 
      The register of ttctrl.ttha describes like below:
- Internal TT Hub Address Representation
- RW
- Default = 0000000b
This field is used to match against the Hub Address field in QH & siTD
to determine if the packet is routed to the internal TT for directly
attached FS/LS devices. If the Hub Address in the QH or siTD does not
match this address then the packet will be broadcast on the High Speed
ports destined for a downstream High Speed hub with the address in the QH/siTD.

In silicon RTL, this entry only affects QH and siTD, and the hub.addr at
both QH and siTD are 0 in ehci core for chipidea (with hcd->has_tt = 1).

So, for QH, if the "usage_tt" flag at RTL is 0, set CI_HDRC_SET_NON_ZERO_TTHA
will not affect QH (with non-hs device); for siTD, set this flag
will change remaining space requirement for the last transaction from 1023
bytes to 188 bytes, it can increase the number of transactions within one
frame, ehci periodic schedule code will not queue the packet if the frame space
is full, so it is safe to set this flag for siTD.

With this flag, it can fix the problem Alan Stern reported below:
http://www.spinics.net/lists/linux-usb/msg123125.html
And may fix Michael Tessier's problem too.
http://www.spinics.net/lists/linux-usb/msg118679.html

CC: stern@rowland.harvard.edu
CC: michael.tessier@axiontech.ca
Signed-off-by: NPeter Chen <peter.chen@freescale.com>
      28362673