Noticed when setting SSP0 in clk_set_rate, _CLK_SET_RATE attempts to
reset the clock divider for the SSP0 parent clock, in this case
IO0FRAC. Bits 24-29 of HW_CLKCTRL_FRAC0 are cleared correctly, but
when the new frac value is written the value isn't shifted up to write
the correct bit-field.  This results in IO0FRAC being set to 0 and
CPUFRAC being corrupted.

This should occur when writing IO1FRAC, EMIFRAC in HW_CLKCTRL_FRAC0
and GPMIFRAC, HSADCFRAC in HW_CLKCTRL_FRAC1.

Tested on custom i.MX28 board with SSP0 SPI driver.
Signed-off-by: NMatt Burtch <matt@grid-net.com>
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>

Added initial support for DENX M28 module and M28EVK
board. Ethernet(FEC), SDHC, Display are supported.
Signed-off-by: NStefano Babic <sbabic@denx.de>
Reviewed-by: NWolfram Sang <w.sang@pengutronix.de>
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>

According to spec, set to 1 is the enable of fractional devide
or the clock can not be generated properly.
Signed-off-by: NDong Aisheng <b29396@freescale.com>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Reviewed-by: NWolfram Sang <w.sang@pengutronix.de>

Set pll0 as parent.
Signed-off-by: NDong Aisheng <b29396@freescale.com>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Reviewed-by: NWolfram Sang <w.sang@pengutronix.de>

For the lcdif clock get_rate looks as follows:

	read div from HW_CLKCTRL_DIS_LCDIF.DIV
	return clk_get_rate(clk->parent) / div

with clk->parent being ref_pix_clk on my system.

ref_pix_clk's rate depends on HW_CLKCTRL_FRAC1.PIXFRAC.

The set_rate function for lcdif does:

	parent_rate = clk_get_rate(clk->parent);
	based on that calculate frac and div such that
	  parent_rate * 18 / frac / div is near the requested rate.
	HW_CLKCTRL_FRAC1.PIXFRAC is updated with frac
	HW_CLKCTRL_DIS_LCDIF.DIV is updated with div

For this calculation to be correct parent_rate needs to be
initialized not with the clock rate of lcdif's parent (i.e. ref_pix) but
that of its grandparent (i.e. ref_pix' parent == pll0_clk).

The obvious downside of this patch is that now set_rate(lcdif) changes
its parent's rate, too.  Still this is better than a wrong rate.
Acked-by: NShawn Guo <shawn.guo@freescale.com>
LAKML-Reference: 20110225084950.GA13684@S2101-09.ap.freescale.net
Signed-off-by: NUwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>

Signed-off-by: NShawn Guo <shawn.guo@freescale.com>
[ukleinek: fix naming to include complete device name in functions]
Signed-off-by: NUwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>

Most likely, the LCD panel on mx28 platform will require a pixel
clock higher than ref_xtal_clk (24 MHz), so the patch initializes
the parent of lcdif clock as ref_pix_clk.
Signed-off-by: NShawn Guo <shawn.guo@freescale.com>
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>

Signed-off-by: NShawn Guo <shawn.guo@freescale.com>
Tested-by: NWolfram Sang <w.sang@pengutronix.de>
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>

Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Cc: Shawn Guo <shawn.guo@freescale.com>

Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: NUwe Kleine-König <u.kleine-koenig@pengutronix.de>

Signed-off-by: NMarc Kleine-Budde <mkl@pengutronix.de>
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>

Commit b2878fa4 (ARM: mx28: update clock and device name for dual fec
support) added only the new lookups without removing the old one.

Cc: Shawn Guo <shawn.guo@freescale.com>
Signed-off-by: NUwe Kleine-König <u.kleine-koenig@pengutronix.de>
Acked-by: NShawn Guo <shawn.guo@freescale.com>
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>

Signed-off-by: NShawn Guo <shawn.guo@freescale.com>
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>

Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>

_CLK_SET_RATE does not only handle the cpu clock but also other
clocks, so do not hardcode the HW_CLKCTRL_CPU register.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Acked-by: NShawn Guo <shawn.guo@freescale.com>

reg | (1 << clk->enable_shift) always evaluates to true. Switch it
to & which makes much more sense
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Acked-by: NShawn Guo <shawn.guo@freescale.com>

Since commit

	6d803ba7 (ARM: 6483/1: arm & sh: factorised duplicated clkdev.c)

platforms need to select CLKDEV_LOOKUP instead of COMMON_CLKDEV and need
to include <linux/clkdev.h>.

Cc: Shawn Guo <shawn.guo@freescale.com>
Cc: Lothar Waßmann <LW@KARO-electronics.de>
Signed-off-by: NUwe Kleine-König <u.kleine-koenig@pengutronix.de>
Acked-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>

The mxs duart is actually an amba-pl011 device. This commit changes
the duart device code to dynamically allocate amba-pl011 device,
so that drivers/serial/amba-pl011.c can be used on mxs.
Signed-off-by: NShawn Guo <shawn.guo@freescale.com>
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>

Change device name from "fec" to "imx28-fec", so that fec driver
can distinguish mx28.
Signed-off-by: NShawn Guo <shawn.guo@freescale.com>
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>

Add clock for MXS-based SoCs, MX23 and MX28.
Signed-off-by: NShawn Guo <shawn.guo@freescale.com>
Signed-off-by: NUwe Kleine-König <u.kleine-koenig@pengutronix.de>