1. 05 11月, 2009 4 次提交
    • T
      pccard: configure CLS on attach · 15ea76d4
      Tejun Heo 提交于
      For non hotplug PCI devices, the system firmware usually configures
      CLS correctly.  For pccard devices system firmware can't do it and
      Linux PCI layer doesn't do it either.  Unfortunately this leads to
      poor performance for certain devices (sata_sil).  Unless MWI, which
      requires separate configuration, is to be used, CLS doesn't affect
      correctness, so the configuration should be harmless.
      
      This patch makes pci_set_cacheline_size() always built and export it
      and make pccard call it during attach.
      
      Please note that some other PCI hotplug drivers (shpchp and pciehp)
      also configure CLS on hotplug.
      Signed-off-by: NTejun Heo <tj@kernel.org>
      Cc: Daniel Ritz <daniel.ritz@gmx.ch>
      Cc: Dominik Brodowski <linux@dominikbrodowski.net>
      Cc: Greg KH <greg@kroah.com>
      Cc: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com>
      Cc: Axel Birndt <towerlexa@gmx.de>
      Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
      15ea76d4
    • T
      sparc64/PCI: drop PCI_CACHE_LINE_BYTES · 4c0eec7a
      Tejun Heo 提交于
      sparc64 is now the only user of PCI_CACHE_LINE_BYTES.  Drop it and set
      pci_dfl_cache_line_size from pcibios_init() instead and drop
      PCI_CACHE_LINE_BYTES handling from generic pci code.
      
      Orignally-From: David Miller <davem@davemloft.net>
      Signed-off-by: NTejun Heo <tj@kernel.org>
      Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
      4c0eec7a
    • J
      PCI: determine CLS more intelligently · ac1aa47b
      Jesse Barnes 提交于
      Till now, CLS has been determined either by arch code or as
      L1_CACHE_BYTES.  Only x86 and ia64 set CLS explicitly and x86 doesn't
      always get it right.  On most configurations, the chance is that
      firmware configures the correct value during boot.
      
      This patch makes pci_init() determine CLS by looking at what firmware
      has configured.  It scans all devices and if all non-zero values
      agree, the value is used.  If none is configured or there is a
      disagreement, pci_dfl_cache_line_size is used.  arch can set the dfl
      value (via PCI_CACHE_LINE_BYTES or pci_dfl_cache_line_size) or
      override the actual one.
      
      ia64, x86 and sparc64 updated to set the default cls instead of the
      actual one.
      
      While at it, declare pci_cache_line_size and pci_dfl_cache_line_size
      in pci.h and drop private declarations from arch code.
      Signed-off-by: NTejun Heo <tj@kernel.org>
      Acked-by: NDavid Miller <davem@davemloft.net>
      Acked-by: NGreg KH <gregkh@suse.de>
      Cc: Ingo Molnar <mingo@elte.hu>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: Tony Luck <tony.luck@intel.com>
      Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
      ac1aa47b
    • Y
      x86/PCI: read root resources from IOH on Intel · 99935a7a
      Yinghai Lu 提交于
      For intel systems with multi IOH, we should read peer root resources
      directly from PCI config space, and don't trust _CRS.
      Signed-off-by: NYinghai Lu <yinghai.lu@sun.com>
      Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
      99935a7a
  2. 04 11月, 2009 14 次提交
  3. 03 11月, 2009 22 次提交