1. 09 10月, 2016 1 次提交
    • H
      parisc: Increase initial kernel mapping size · 65bf34f5
      Helge Deller 提交于
      Increase the initial kernel default page mapping size for 64-bit kernels to
      64 MB and for 32-bit kernels to 32 MB.
      
      Due to the additional support of ftrace, tracepoint and huge pages the kernel
      size can exceed the sizes we used up to now.
      
      Cc: stable@vger.kernel.org # 4.4+
      Signed-off-by: NHelge Deller <deller@gmx.de>
      65bf34f5
  2. 08 10月, 2016 1 次提交
    • H
      parisc: Increase KERNEL_INITIAL_SIZE for 32-bit SMP kernels · 690d097c
      Helge Deller 提交于
      Increase the initial kernel default page mapping size for SMP kernels to 32MB
      and add a runtime check which panics early if the kernel is bigger than the
      initial mapping size.
      
      This fixes boot crashes of 32bit SMP kernels. Due to the introduction of huge
      page support in kernel 4.4 and it's required initial kernel layout in memory, a
      32bit SMP kernel usually got bigger (in layout, not size) than 16MB.
      
      Cc: stable@vger.kernel.org #4.4+
      Signed-off-by: NHelge Deller <deller@gmx.de>
      690d097c
  3. 12 12月, 2015 1 次提交
  4. 22 11月, 2015 2 次提交
    • H
      parisc: Increase initial kernel mapping to 32MB on 64bit kernel · 332b42e4
      Helge Deller 提交于
      For the 64bit kernel the initially 16 MB kernel memory might become too
      small if you build a kernel with many modules built-in and with kernel
      text and data areas mapped on huge pages.
      
      This patch increases the initial mapping to 32MB for 64bit kernels and
      keeps 16MB for 32bit kernels.
      Signed-off-by: NHelge Deller <deller@gmx.de>
      332b42e4
    • H
      parisc: Add defines for Huge page support · 1f25ad26
      Helge Deller 提交于
      Huge pages on parisc will have the same size as one pmd table, which
      is on a 64bit kernel 2MB on a kernel with 4K kernel page sizes, and
      on a 32bit kernel 4MB when used with 4K kernel pages.
      
      Since parisc does not physically supports 2MB huge page sizes, emulate
      it with two consecutive 1MB page sizes instead. Keeping the same huge
      page size as one pmd will allow us to add transparent huge page support
      later on.
      
      Bit 21 in the pte flags was unused and will now be used to mark a page
      as huge page (_PAGE_HPAGE_BIT).
      Signed-off-by: NHelge Deller <deller@gmx.de>
      1f25ad26
  5. 11 7月, 2015 1 次提交
    • J
      parisc: Fix some PTE/TLB race conditions and optimize __flush_tlb_range based on timing results · 01ab6057
      John David Anglin 提交于
      The increased use of pdtlb/pitlb instructions seemed to increase the
      frequency of random segmentation faults building packages. Further, we
      had a number of cases where TLB inserts would repeatedly fail and all
      forward progress would stop. The Haskell ghc package caused a lot of
      trouble in this area. The final indication of a race in pte handling was
      this syslog entry on sibaris (C8000):
      
       swap_free: Unused swap offset entry 00000004
       BUG: Bad page map in process mysqld  pte:00000100 pmd:019bbec5
       addr:00000000ec464000 vm_flags:00100073 anon_vma:0000000221023828 mapping: (null) index:ec464
       CPU: 1 PID: 9176 Comm: mysqld Not tainted 4.0.0-2-parisc64-smp #1 Debian 4.0.5-1
       Backtrace:
        [<0000000040173eb0>] show_stack+0x20/0x38
        [<0000000040444424>] dump_stack+0x9c/0x110
        [<00000000402a0d38>] print_bad_pte+0x1a8/0x278
        [<00000000402a28b8>] unmap_single_vma+0x3d8/0x770
        [<00000000402a4090>] zap_page_range+0xf0/0x198
        [<00000000402ba2a4>] SyS_madvise+0x404/0x8c0
      
      Note that the pte value is 0 except for the accessed bit 0x100. This bit
      shouldn't be set without the present bit.
      
      It should be noted that the madvise system call is probably a trigger for many
      of the random segmentation faults.
      
      In looking at the kernel code, I found the following problems:
      
      1) The pte_clear define didn't take TLB lock when clearing a pte.
      2) We didn't test pte present bit inside lock in exception support.
      3) The pte and tlb locks needed to merged in order to ensure consistency
      between page table and TLB. This also has the effect of serializing TLB
      broadcasts on SMP systems.
      
      The attached change implements the above and a few other tweaks to try
      to improve performance. Based on the timing code, TLB purges are very
      slow (e.g., ~ 209 cycles per page on rp3440). Thus, I think it
      beneficial to test the split_tlb variable to avoid duplicate purges.
      Probably, all PA 2.0 machines have combined TLBs.
      
      I dropped using __flush_tlb_range in flush_tlb_mm as I realized all
      applications and most threads have a stack size that is too large to
      make this useful. I added some comments to this effect.
      
      Since implementing 1 through 3, I haven't had any random segmentation
      faults on mx3210 (rp3440) in about one week of building code and running
      as a Debian buildd.
      Signed-off-by: NJohn David Anglin <dave.anglin@bell.net>
      Cc: stable@vger.kernel.org # v3.18+
      Signed-off-by: NHelge Deller <deller@gmx.de>
      01ab6057
  6. 15 4月, 2015 1 次提交
  7. 01 3月, 2015 1 次提交
    • K
      mm: add missing __PAGETABLE_{PUD,PMD}_FOLDED defines · c07af4f1
      Kirill A. Shutemov 提交于
      Core mm expects __PAGETABLE_{PUD,PMD}_FOLDED to be defined if these page
      table levels folded.  Usually, these defines are provided by
      <asm-generic/pgtable-nopmd.h> and <asm-generic/pgtable-nopud.h>.
      
      But some architectures fold page table levels in a custom way.  They
      need to define these macros themself.  This patch adds missing defines.
      
      The patch fixes mm->nr_pmds underflow and eliminates dead __pmd_alloc()
      and __pud_alloc() on architectures without these page table levels.
      Signed-off-by: NKirill A. Shutemov <kirill.shutemov@linux.intel.com>
      Cc: Aaro Koskinen <aaro.koskinen@iki.fi>
      Cc: David Howells <dhowells@redhat.com>
      Cc: Geert Uytterhoeven <geert@linux-m68k.org>
      Cc: Heiko Carstens <heiko.carstens@de.ibm.com>
      Cc: Helge Deller <deller@gmx.de>
      Cc: "James E.J. Bottomley" <jejb@parisc-linux.org>
      Cc: Koichi Yasutake <yasutake.koichi@jp.panasonic.com>
      Cc: Martin Schwidefsky <schwidefsky@de.ibm.com>
      Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
      Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      c07af4f1
  8. 12 2月, 2015 1 次提交
  9. 11 2月, 2015 1 次提交
  10. 03 2月, 2014 1 次提交
  11. 29 6月, 2013 1 次提交
  12. 26 4月, 2013 1 次提交
    • J
      parisc: use spin_lock_irqsave/spin_unlock_irqrestore for PTE updates · bda079d3
      John David Anglin 提交于
      User applications running on SMP kernels have long suffered from instability
      and random segmentation faults.  This patch improves the situation although
      there is more work to be done.
      
      One of the problems is the various routines in pgtable.h that update page table
      entries use different locking mechanisms, or no lock at all (set_pte_at).  This
      change modifies the routines to all use the same lock pa_dbit_lock.  This lock
      is used for dirty bit updates in the interruption code. The patch also purges
      the TLB entries associated with the PTE to ensure that inconsistent values are
      not used after the page table entry is updated.  The UP and SMP code are now
      identical.
      
      The change also includes a minor update to the purge_tlb_entries function in
      cache.c to improve its efficiency.
      Signed-off-by: NJohn David Anglin <dave.anglin@bell.net>
      Cc: Helge Deller <deller@gmx.de>
      Signed-off-by: NHelge Deller <deller@gmx.de>
      bda079d3
  13. 19 1月, 2013 1 次提交
  14. 11 5月, 2012 1 次提交
  15. 16 4月, 2011 1 次提交
    • J
      [PARISC] only make executable areas executable · d7dd2ff1
      James Bottomley 提交于
      Currently parisc has the whole kernel marked as RWX, meaning any
      kernel page at all is eligible to be executed.  This can cause a
      theoretical problem on systems with combined I/D TLB because the act
      of referencing a page causes a TLB insertion with an executable bit.
      This TLB entry may be used by the CPU as the basis for speculating the
      page into the I-Cache.  If this speculated page is subsequently used
      for a user process, there is the possibility we will get a stale
      I-cache line picked up as the binary executes.
      
      As a point of good practise, only mark actual kernel text pages as
      executable.  The same has to be done for init_text pages, but they're
      converted to data pages (and the I-Cache flushed) when the init memory
      is released.
      Signed-off-by: NJames Bottomley <James.Bottomley@suse.de>
      d7dd2ff1
  16. 17 1月, 2011 1 次提交
  17. 15 1月, 2011 2 次提交
  18. 27 10月, 2010 1 次提交
  19. 21 2月, 2010 1 次提交
    • R
      MM: Pass a PTE pointer to update_mmu_cache() rather than the PTE itself · 4b3073e1
      Russell King 提交于
      On VIVT ARM, when we have multiple shared mappings of the same file
      in the same MM, we need to ensure that we have coherency across all
      copies.  We do this via make_coherent() by making the pages
      uncacheable.
      
      This used to work fine, until we allowed highmem with highpte - we
      now have a page table which is mapped as required, and is not available
      for modification via update_mmu_cache().
      
      Ralf Beache suggested getting rid of the PTE value passed to
      update_mmu_cache():
      
        On MIPS update_mmu_cache() calls __update_tlb() which walks pagetables
        to construct a pointer to the pte again.  Passing a pte_t * is much
        more elegant.  Maybe we might even replace the pte argument with the
        pte_t?
      
      Ben Herrenschmidt would also like the pte pointer for PowerPC:
      
        Passing the ptep in there is exactly what I want.  I want that
        -instead- of the PTE value, because I have issue on some ppc cases,
        for I$/D$ coherency, where set_pte_at() may decide to mask out the
        _PAGE_EXEC.
      
      So, pass in the mapped page table pointer into update_mmu_cache(), and
      remove the PTE value, updating all implementations and call sites to
      suit.
      
      Includes a fix from Stephen Rothwell:
      
        sparc: fix fallout from update_mmu_cache API change
      Signed-off-by: NStephen Rothwell <sfr@canb.auug.org.au>
      Acked-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      4b3073e1
  20. 31 3月, 2009 1 次提交
    • H
      parisc: fix usage of 32bit PTE page table entries on 32bit kernels · 48d27cb2
      Helge Deller 提交于
      This patch fixes a long outstanding bug on 32bit parisc linux kernels
      which prevented us from using 32bit PTE table entries (instead of 64bit
      entries of which 32bit were unused).
      
      The problem was caused by this assembler statement in the L2_ptep
      macro in arch/parisc/kernel/entry.S:447:
      	EXTR \va,31-ASM_PGDIR_SHIFT,ASM_BITS_PER_PGD,\index
      which expanded to
      	extrw,u r8,9,11,r1
      and which has undefined behavior since the length value (11) extends
      beyond the leftmost bit (11-1 > 9).
      Interestingly PA2.0 processors seem to don't care and just zero-extend
      the value, while PA1.1 processors don't.
      
      Fix this problem by detecting an address space overflow with ASM_BITS_PER_PGD
      and adjusting it accordingly. To prevent such problems in the future,
      some compile time sanity checks in arch/parisc/mm/init.c were added.
      
      Since the page table now only consumes half of it's old size, we can
      use the freed memory to harmonize 32- and 64bit kernels and let both
      map 16MB for the initial page table.
      Signed-off-by: NHelge Deller <deller@gmx.de>
      Signed-off-by: NKyle McMartin <kyle@mcmartin.ca>
      48d27cb2
  21. 11 10月, 2008 1 次提交
  22. 28 4月, 2008 1 次提交
    • N
      mm: introduce pte_special pte bit · 7e675137
      Nick Piggin 提交于
      s390 for one, cannot implement VM_MIXEDMAP with pfn_valid, due to their memory
      model (which is more dynamic than most).  Instead, they had proposed to
      implement it with an additional path through vm_normal_page(), using a bit in
      the pte to determine whether or not the page should be refcounted:
      
      vm_normal_page()
      {
      	...
              if (unlikely(vma->vm_flags & (VM_PFNMAP|VM_MIXEDMAP))) {
                      if (vma->vm_flags & VM_MIXEDMAP) {
      #ifdef s390
      			if (!mixedmap_refcount_pte(pte))
      				return NULL;
      #else
                              if (!pfn_valid(pfn))
                                      return NULL;
      #endif
                              goto out;
                      }
      	...
      }
      
      This is fine, however if we are allowed to use a bit in the pte to determine
      refcountedness, we can use that to _completely_ replace all the vma based
      schemes.  So instead of adding more cases to the already complex vma-based
      scheme, we can have a clearly seperate and simple pte-based scheme (and get
      slightly better code generation in the process):
      
      vm_normal_page()
      {
      #ifdef s390
      	if (!mixedmap_refcount_pte(pte))
      		return NULL;
      	return pte_page(pte);
      #else
      	...
      #endif
      }
      
      And finally, we may rather make this concept usable by any architecture rather
      than making it s390 only, so implement a new type of pte state for this.
      Unfortunately the old vma based code must stay, because some architectures may
      not be able to spare pte bits.  This makes vm_normal_page a little bit more
      ugly than we would like, but the 2 cases are clearly seperate.
      
      So introduce a pte_special pte state, and use it in mm/memory.c.  It is
      currently a noop for all architectures, so this doesn't actually result in any
      compiled code changes to mm/memory.o.
      
      BTW:
      I haven't put vm_normal_page() into arch code as-per an earlier suggestion.
      The reason is that, regardless of where vm_normal_page is actually
      implemented, the *abstraction* is still exactly the same. Also, while it
      depends on whether the architecture has pte_special or not, that is the
      only two possible cases, and it really isn't an arch specific function --
      the role of the arch code should be to provide primitive functions and
      accessors with which to build the core code; pte_special does that. We do
      not want architectures to know or care about vm_normal_page itself, and
      we definitely don't want them being able to invent something new there
      out of sight of mm/ code. If we made vm_normal_page an arch function, then
      we have to make vm_insert_mixed (next patch) an arch function too. So I
      don't think moving it to arch code fundamentally improves any abstractions,
      while it does practically make the code more difficult to follow, for both
      mm and arch developers, and easier to misuse.
      
      [akpm@linux-foundation.org: build fix]
      Signed-off-by: NNick Piggin <npiggin@suse.de>
      Acked-by: NCarsten Otte <cotte@de.ibm.com>
      Cc: Jared Hulbert <jaredeh@gmail.com>
      Cc: Martin Schwidefsky <schwidefsky@de.ibm.com>
      Cc: Heiko Carstens <heiko.carstens@de.ibm.com>
      Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
      Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      7e675137
  23. 16 3月, 2008 1 次提交
  24. 20 10月, 2007 1 次提交
  25. 18 10月, 2007 2 次提交
  26. 18 7月, 2007 1 次提交
  27. 17 7月, 2007 1 次提交
  28. 09 5月, 2007 1 次提交
  29. 17 2月, 2007 1 次提交
  30. 26 9月, 2006 1 次提交
    • D
      [PATCH] Standardize pxx_page macros · 46a82b2d
      Dave McCracken 提交于
      One of the changes necessary for shared page tables is to standardize the
      pxx_page macros.  pte_page and pmd_page have always returned the struct
      page associated with their entry, while pte_page_kernel and pmd_page_kernel
      have returned the kernel virtual address.  pud_page and pgd_page, on the
      other hand, return the kernel virtual address.
      
      Shared page tables needs pud_page and pgd_page to return the actual page
      structures.  There are very few actual users of these functions, so it is
      simple to standardize their usage.
      
      Since this is basic cleanup, I am submitting these changes as a standalone
      patch.  Per Hugh Dickins' comments about it, I am also changing the
      pxx_page_kernel macros to pxx_page_vaddr to clarify their meaning.
      Signed-off-by: NDave McCracken <dmccr@us.ibm.com>
      Cc: Hugh Dickins <hugh@veritas.com>
      Signed-off-by: NAndrew Morton <akpm@osdl.org>
      Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      46a82b2d
  31. 28 6月, 2006 1 次提交
  32. 26 4月, 2006 1 次提交
  33. 22 4月, 2006 1 次提交
  34. 23 1月, 2006 1 次提交
  35. 07 11月, 2005 1 次提交
  36. 22 10月, 2005 1 次提交
  37. 13 9月, 2005 1 次提交