- 23 8月, 2012 1 次提交
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由 Vijay Purushothaman 提交于
This is already fixed for ILK and SNB in the below commit but somehow IVB is missed. commit ab2f9df1 Author: Jesse Barnes <jbarnes@virtuousgeek.org> Date: Mon Feb 27 12:40:10 2012 -0800 drm/i915: fix color order for BGR formats on SNB Had the wrong bits and field definitions. Signed-off-by: NVijay Purushothaman <vijay.a.purushothaman@intel.com> Reviewed-by: NAntti Koskipää <antti.koskipaa@linux.intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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- 20 7月, 2012 1 次提交
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Or going from tiled to untiled may break. Signed-off-by: NAnder Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Reviewed-by: NChris Wilson <chris@chris-wilson.co.uk> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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- 27 6月, 2012 3 次提交
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由 Jesper Juhl 提交于
If we ever hit the default case in the switch statement we'll return from the function without freeing the memory we just allocated to 'intel_plane' (but that has not been used). This patch gets rid of the leak by freeing the memory just before we return. Signed-off-by: NJesper Juhl <jj@chaosbits.net> Reviewed-by: NJesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Jesse Barnes 提交于
We shouldn't hit this path anyway, but make it use the IVB sprite format definition to avoid confusion. Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Jesse Barnes 提交于
Or going from tiled to untiled may break. Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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- 14 6月, 2012 1 次提交
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由 Chris Wilson 提交于
As we switch on/off the primary plane if it is completely obscured by an overlapping video sprite, we also nee to make sure that we update the FBC configuration at the same time. v2: Not all crtcs are intel_crtcs, as spotted by Daniel. v3: Boot testing rules. References: https://bugs.freedesktop.org/show_bug.cgi?id=50238Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk> Cc: Jesse Barnes <jbarnes@virtuousgeek.org> Reviewed-by: NJesse Barnes <jbarnes@virtuousgeek.org> Reviewed-by: NJani Nikula <jani.nikula@linux.intel.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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- 03 5月, 2012 2 次提交
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由 Daniel Vetter 提交于
Also ditch the cargo-culted dev_priv checks - either we have a giant hole in our setup code or this is useless. Plainly bogus to check for it in either case. v2: Chris Wilson noticed that I've missed one bogus dev_priv check. v3: The check in the overlay code is redundant (Chris) Reviewed-by: NChris Wilson <chris@chris-wilson.co.uk> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Chris Wilson 提交于
IvyBridge requires an extra frame between disabling the low power watermarks and enabling scaling on the sprite plane. If the scaling is already enabled, then we have already disabled the low power watermarks and need not incur an extra wait. Similarly, as we disable the scaling when turning off the sprite plane, we can update the scaling enabled flag and restore the low power watermarks. Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk> Reviewed-by: NJesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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- 17 4月, 2012 3 次提交
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由 Armin Reese 提交于
The purpose of this patch is to avoid zeroing the lower 12 reserved bits of surface base address registers (framebuffer & sprite). There are bits in that range that may occasionally be set by BIOS or by other components. Signed-off-by: NArmin Reese <armin.c.reese@intel.com> Reviewed-by: NJesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Chris Wilson 提交于
As I do not see the output update without the scaler enabled on my i3-330m, always enable it. Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk> Acked-by: NJesse Barnes <jbarnes@virtuousgeek.org> Signed-Off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Chris Wilson 提交于
Rather than export every single architecture specific update_wm, just export the wrapper around the display vtable. Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk> Reviewed-by: NJesse Barnes <jbarnes@virtuousgeek.org> Signed-Off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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- 13 4月, 2012 1 次提交
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由 Chris Wilson 提交于
Well, almost. Just a couple of differences, Ironlake lacks a few of the RGB formats, only exposing x8r8g8b8, and lacks a couple of unused features. Given the similarities, we can then reuse the same routines as already written for Sandybridge to enable overlay support for Ironlake as well. Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk> Reviewed-by: NJesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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- 10 4月, 2012 1 次提交
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由 acreese 提交于
The destination color key is always enabled for IVB. Removed the line that does this. Signed-off-by: NArmin Reese <armin.c.reese@intel.com> Acked-by: NJesse Barnes <jbarnes@virtuousgeek.org> Cc: stable@kernel.org Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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- 03 4月, 2012 1 次提交
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由 Jesse Barnes 提交于
This was missed when we converted the source values to 16.16 fixed point. Cc: stable@vger.kernel.org Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org> Tested-by: NChris Wilson <chris@chris-wilson.co.uk> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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- 08 3月, 2012 1 次提交
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由 Jesse Barnes 提交于
Had the wrong bits and field definitions. Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: NKeith Packard <keithp@keithp.com>
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- 30 1月, 2012 1 次提交
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由 Chris Wilson 提交于
In order to correctly account for reserving space in the GTT and fences for a batch buffer, we need to independently track whether the fence is pinned due to a fenced GPU access in the batch or whether the buffer is pinned in the aperture. Currently we count the fenced as pinned if the buffer has already been seen in the execbuffer. This leads to a false accounting of available fence registers, causing frequent mass evictions. Worse, if coupled with the change to make i915_gem_object_get_fence() report EDADLK upon fence starvation, the batchbuffer can fail with only one fence required... Fixes intel-gpu-tools/tests/gem_fenced_exec_thrash Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=38735Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk> Reviewed-by: NDaniel Vetter <daniel.vetter@ffwll.ch> Tested-by: NPaul Neumann <paul104x@yahoo.de> [danvet: Resolve the functional conflict with Jesse Barnes sprite patches, acked by Chris Wilson on irc.] Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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- 14 1月, 2012 1 次提交
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由 Jesse Barnes 提交于
We can call the plane init function unconditionally, but don't need to complain if it fails, since that will only happen if we're out of memory (and other things will fail) or if we're on the wrong platform (which is ok). And remove the DRM_ERRORs from the sprite code itself to avoid dmesg spam. Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org> Reviewed-by: NKeith Packard <keithp@keithp.com> Signed-off-by: NKeith Packard <keithp@keithp.com>
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- 05 1月, 2012 1 次提交
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由 Rob Clark 提交于
In cases where the scanout hw is sufficiently similar between "overlay" and traditional crtc layers, it might be convenient to allow the driver to create internal drm_plane helper objects used by the drm_crtc implementation, rather than duplicate code between the plane and crtc. A private plane is not exposed to userspace. Signed-off-by: NRob Clark <rob@ti.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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- 04 1月, 2012 3 次提交
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由 Jesse Barnes 提交于
Add new ioctls for getting and setting the current destination color key. This allows for simple overlay display control by matching a color key value in the primary plane before blending the overlay on top. v2: remove unnecessary mutex acquire/release around reg accesses v3: add support for full color key management v4: fix copy & paste bug in snb_get_colorkey don't bother checking min/max values against docs as the docs are likely wrong (how could we handle 10bpc surface formats?) Reviewed-by: NDaniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
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由 Jesse Barnes 提交于
To save power when the sprite is full screen, we can disable the primary plane on the same pipe. Track the sprite status and enable/disable the primary opportunistically. v2: remove primary plane enable/disable hooks; they're identical Reviewed-by: NDaniel Vetter <daniel@ffwll.ch> Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: NKeith Packard <keithp@keithp.com>
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由 Jesse Barnes 提交于
The video sprites support various video surface formats natively and can handle scaling as well. So add support for them using the new DRM core sprite support functions. v2: use drm specific fourcc header and defines v3: address Daniel's comments: - don't take struct mutex around register access (only needed for regs in the GT power well) - don't hold struct mutex across vblank waits - fix up update_plane API (pass obj instead of GTT offset) - add interlaced defines for sprite regs - drop unnecessary 'reg' variables - comment double buffered reg flushing Also fix w/h confusion when writing the scaling reg. v4: more fixes, address more comments from Daniel, and include Hai's fix - prevent divide by zero in scaling calculation (Hai Lan) - update to Ville's new DRM_FORMAT_* types - fix sprite watermark handling (calc based on CRTC size, separate from normal display wm) - remove private refcounts now that the fb cleanups handles things v5: add linear surface support v6: remove color key clearing & setting from update_plane For this version, I tested DPMS since it came up in the last review; DPMS off/on works ok when a video player is working under X, but for power saving we'll probably want to do something smarter. I'll leave that for a separate patch on top. Likewise with the refcounting/fb layer handling, which are really separate cleanups. Reviewed-by: NDaniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: NKeith Packard <keithp@keithp.com>
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