1. 12 7月, 2011 3 次提交
    • L
      KVM: PPC: e500: Add shadow PID support · dd9ebf1f
      Liu Yu 提交于
      Dynamically assign host PIDs to guest PIDs, splitting each guest PID into
      multiple host (shadow) PIDs based on kernel/user and MSR[IS/DS].  Use
      both PID0 and PID1 so that the shadow PIDs for the right mode can be
      selected, that correspond both to guest TID = zero and guest TID = guest
      PID.
      
      This allows us to significantly reduce the frequency of needing to
      invalidate the entire TLB.  When the guest mode or PID changes, we just
      update the host PID0/PID1.  And since the allocation of shadow PIDs is
      global, multiple guests can share the TLB without conflict.
      
      Note that KVM does not yet support the guest setting PID1 or PID2 to
      a value other than zero.  This will need to be fixed for nested KVM
      to work.  Until then, we enforce the requirement for guest PID1/PID2
      to stay zero by failing the emulation if the guest tries to set them
      to something else.
      Signed-off-by: NLiu Yu <yu.liu@freescale.com>
      Signed-off-by: NScott Wood <scottwood@freescale.com>
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      dd9ebf1f
    • S
      KVM: PPC: e500: Save/restore SPE state · 4cd35f67
      Scott Wood 提交于
      This is done lazily.  The SPE save will be done only if the guest has
      used SPE since the last preemption or heavyweight exit.  Restore will be
      done only on demand, when enabling MSR_SPE in the shadow MSR, in response
      to an SPE fault or mtmsr emulation.
      
      For SPEFSCR, Linux already switches it on context switch (non-lazily), so
      the only remaining bit is to save it between qemu and the guest.
      Signed-off-by: NLiu Yu <yu.liu@freescale.com>
      Signed-off-by: NScott Wood <scottwood@freescale.com>
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      4cd35f67
    • S
      KVM: PPC: booke: use shadow_msr · ecee273f
      Scott Wood 提交于
      Keep the guest MSR and the guest-mode true MSR separate, rather than
      modifying the guest MSR on each guest entry to produce a true MSR.
      
      Any bits which should be modified based on guest MSR must be explicitly
      propagated from vcpu->arch.shared->msr to vcpu->arch.shadow_msr in
      kvmppc_set_msr().
      
      While we're modifying the guest entry code, reorder a few instructions
      to bury some load latencies.
      Signed-off-by: NScott Wood <scottwood@freescale.com>
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      ecee273f
  2. 22 5月, 2011 2 次提交
  3. 11 5月, 2011 1 次提交
    • B
      KVM: PPC: Fix issue clearing exit timing counters · 09000adb
      Bharat Bhushan 提交于
      Following dump is observed on host when clearing the exit timing counters
      
      [root@p1021mds kvm]# echo -n 'c' > vm1200_vcpu0_timing
      INFO: task echo:1276 blocked for more than 120 seconds.
      "echo 0 > /proc/sys/kernel/hung_task_timeout_secs" disables this message.
      echo          D 0ff5bf94     0  1276   1190 0x00000000
      Call Trace:
      [c2157e40] [c0007908] __switch_to+0x9c/0xc4
      [c2157e50] [c040293c] schedule+0x1b4/0x3bc
      [c2157e90] [c04032dc] __mutex_lock_slowpath+0x74/0xc0
      [c2157ec0] [c00369e4] kvmppc_init_timing_stats+0x20/0xb8
      [c2157ed0] [c0036b00] kvmppc_exit_timing_write+0x84/0x98
      [c2157ef0] [c00b9f90] vfs_write+0xc0/0x16c
      [c2157f10] [c00ba284] sys_write+0x4c/0x90
      [c2157f40] [c000e320] ret_from_syscall+0x0/0x3c
      
              The vcpu->mutex is used by kvm_ioctl_* (KVM_RUN etc) and same was
      used when clearing the stats (in kvmppc_init_timing_stats()). What happens
      is that when the guest is idle then it held the vcpu->mutx. While the
      exiting timing process waits for guest to release the vcpu->mutex and
      a hang state is reached.
      
              Now using seprate lock for exit timing stats.
      Signed-off-by: NBharat Bhushan <Bharat.Bhushan@freescale.com>
      Acked-by: NAlexander Graf <agraf@suse.de>
      Signed-off-by: NAvi Kivity <avi@redhat.com>
      09000adb
  4. 24 10月, 2010 9 次提交
    • A
      KVM: PPC: Add book3s_32 tlbie flush acceleration · 2d27fc5e
      Alexander Graf 提交于
      On Book3s_32 the tlbie instruction flushed effective addresses by the mask
      0x0ffff000. This is pretty hard to reflect with a hash that hashes ~0xfff, so
      to speed up that target we should also keep a special hash around for it.
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      Signed-off-by: NAvi Kivity <avi@redhat.com>
      2d27fc5e
    • A
      KVM: PPC: RCU'ify the Book3s MMU · 2e0908af
      Alexander Graf 提交于
      So far we've been running all code without locking of any sort. This wasn't
      really an issue because I didn't see any parallel access to the shadow MMU
      code coming.
      
      But then I started to implement dirty bitmapping to MOL which has the video
      code in its own thread, so suddenly we had the dirty bitmap code run in
      parallel to the shadow mmu code. And with that came trouble.
      
      So I went ahead and made the MMU modifying functions as parallelizable as
      I could think of. I hope I didn't screw up too much RCU logic :-). If you
      know your way around RCU and locking and what needs to be done when, please
      take a look at this patch.
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      Signed-off-by: NAvi Kivity <avi@redhat.com>
      2e0908af
    • A
      KVM: PPC: First magic page steps · beb03f14
      Alexander Graf 提交于
      We will be introducing a method to project the shared page in guest context.
      As soon as we're talking about this coupling, the shared page is colled magic
      page.
      
      This patch introduces simple defines, so the follow-up patches are easier to
      read.
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      Signed-off-by: NAvi Kivity <avi@redhat.com>
      beb03f14
    • A
      KVM: PPC: Make PAM a define · 28e83b4f
      Alexander Graf 提交于
      On PowerPC it's very normal to not support all of the physical RAM in real mode.
      To check if we're matching on the shared page or not, we need to know the limits
      so we can restrain ourselves to that range.
      
      So let's make it a define instead of open-coding it. And while at it, let's also
      increase it.
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      
      v2 -> v3:
      
        - RMO -> PAM (non-magic page)
      Signed-off-by: NAvi Kivity <avi@redhat.com>
      28e83b4f
    • A
      KVM: PPC: Convert SPRG[0-4] to shared page · a73a9599
      Alexander Graf 提交于
      When in kernel mode there are 4 additional registers available that are
      simple data storage. Instead of exiting to the hypervisor to read and
      write those, we can just share them with the guest using the page.
      
      This patch converts all users of the current field to the shared page.
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      Signed-off-by: NAvi Kivity <avi@redhat.com>
      a73a9599
    • A
      KVM: PPC: Convert SRR0 and SRR1 to shared page · de7906c3
      Alexander Graf 提交于
      The SRR0 and SRR1 registers contain cached values of the PC and MSR
      respectively. They get written to by the hypervisor when an interrupt
      occurs or directly by the kernel. They are also used to tell the rfi(d)
      instruction where to jump to.
      
      Because it only gets touched on defined events that, it's very simple to
      share with the guest. Hypervisor and guest both have full r/w access.
      
      This patch converts all users of the current field to the shared page.
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      Signed-off-by: NAvi Kivity <avi@redhat.com>
      de7906c3
    • A
      KVM: PPC: Convert DAR to shared page. · 5e030186
      Alexander Graf 提交于
      The DAR register contains the address a data page fault occured at. This
      register behaves pretty much like a simple data storage register that gets
      written to on data faults. There is no hypervisor interaction required on
      read or write.
      
      This patch converts all users of the current field to the shared page.
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      Signed-off-by: NAvi Kivity <avi@redhat.com>
      5e030186
    • A
      KVM: PPC: Convert MSR to shared page · 666e7252
      Alexander Graf 提交于
      One of the most obvious registers to share with the guest directly is the
      MSR. The MSR contains the "interrupts enabled" flag which the guest has to
      toggle in critical sections.
      
      So in order to bring the overhead of interrupt en- and disabling down, let's
      put msr into the shared page. Keep in mind that even though you can fully read
      its contents, writing to it doesn't always update all state. There are a few
      safe fields that don't require hypervisor interaction. See the documentation
      for a list of MSR bits that are safe to be set from inside the guest.
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      Signed-off-by: NAvi Kivity <avi@redhat.com>
      666e7252
    • A
      KVM: PPC: Introduce shared page · 96bc451a
      Alexander Graf 提交于
      For transparent variable sharing between the hypervisor and guest, I introduce
      a shared page. This shared page will contain all the registers the guest can
      read and write safely without exiting guest context.
      
      This patch only implements the stubs required for the basic structure of the
      shared page. The actual register moving follows.
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      Signed-off-by: NAvi Kivity <avi@redhat.com>
      96bc451a
  5. 01 8月, 2010 2 次提交
  6. 17 5月, 2010 6 次提交
  7. 25 4月, 2010 3 次提交
  8. 01 3月, 2010 5 次提交
  9. 05 11月, 2009 2 次提交
  10. 10 9月, 2009 2 次提交
  11. 05 8月, 2009 1 次提交
  12. 24 3月, 2009 4 次提交