The base address of the second memory region on the lager
board is 0x140000000. Update the tag used in the dts file accordingly.

This is a documentation fix and should have no run-time affect.

This problem was introduced when the second memory region
was added to the lager dts file by 62bc32a2
("ARM: shmobile: Include all 4 GiB of memory on Lager)"
in v3.14.
Reported-by: NNAOYA SHIIBA <naoya.shiiba.nx@renesas.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Add the Lager board specific device node part for VIN1 (composite video in);
add the device node for Analog Devices ADV7180 video decoder to IIC2 bus.
Add the necessary subnodes to interconnect VIN1 and ADV7180 devices.
Signed-off-by: NBen Dooks <ben.dooks@codethink.co.uk>
[Sergei: rebased, edited changelog and summary]
Signed-off-by: NSergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

On Lager board, i2c and iic cores can be interchanged since they can be
muxed to the same wires. Commit e489c2a9
("ARM: shmobile: lager: enable i2c devices") activated the i2c cores,
yet the iic cores should be default since they have the more interesting
features for generic use cases, i.e. SMBUS_QUICK and DMA (yet to be
supported).
Reported-by: NKhiem Nguyen <khiem.nguyen.xt@renesas.com>
Signed-off-by: NWolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

I2C bus for VDD MPU regulator is IIC3, not I2C3.
Signed-off-by: NKhiem Nguyen <khiem.nguyen.xt@renesas.com>
Reviewed-by: NWolfram Sang <wsa@sang-engineering.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Enable internal AHB-PCI bridges for the USB EHCI/OHCI controllers attached to
them.
Signed-off-by: NBen Dooks <ben.dooks@codethink.co.uk>
Reviewed-by: NIan Molton <ian.molton@codethink.co.uk>
[Sergei: enabled PCI0]
Signed-off-by: NSergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Tested-by: NYoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Due to an error when merging df40f256b18300e1 ("ARM: shmobile:
lager: add i2c1, i2c2 pins") a duplicate i2c3 node.

This patch moves the duplicate and moves to old node to
be closer to the other new i2c nodes.

Cc: Ben Dooks <ben.dooks@codethink.co.uk>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Update the Lager DTS to make use of the new unified legacy
memory map where the legacy window on Lager and Koelsch
have the same size.

With this change in place the code gets aligned with the
documentation.

After update the Lager board has the following map:
Bank0: 1GiB RAM (Legacy 32-bit: 0x40000000->0x7fffffff)
Bank1: 3GiB RAM (LPAE area: 0x140000000->0x1ffffffff)

Before the update the old map looked like this:
Bank0: 2GiB RAM (Legacy 32-bit: 0x40000000->0xbfffffff)
Bank1: 2GiB RAM (LPAE area: 0x180000000->0x1ffffffff)

Tested with and without LPAE on r8a7790 Lager.
Signed-off-by: NMagnus Damm <damm+renesas@opensource.se>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Due to an error when resolving conflicts df40f256b18300e1 ("ARM: shmobile:
lager: add i2c1, i2c2 pins") added the i2c[12]_pins nodes to the wrong
node.

This patch moves them to their correct location in the pfc node.

Cc: Ben Dooks <ben.dooks@codethink.co.uk>
Reported-by: NSergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Add pinctrl definitions for i2c1 and i2c2 busses on the Lager board
to ensure these are setup correctly at initialisation time. The i2c0
and i2c3 busses are connected to single function pins.
Signed-off-by: NBen Dooks <ben.dooks@codethink.co.uk>
[horms+renesas@verge.net.au: Added shmobile to patch title]
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Add i2c0, i2c1, i2c2 and i2c3 nodes to the Lager reference device tree as
these busses all have devices on them that can be probed even if they
are no drivers yet.
Signed-off-by: NBen Dooks <ben.dooks@codethink.co.uk>
[horms+renesas@verge.net.au: Added shmobile to title]
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Add needed information inside CPU0 for the generic cpufreq-cpu0 driver.

- voltage-tolerance = 1%
  It reflects the tolerance for the CPU voltage defined inside the OPP
  table. Due to the lack of proper OPP definition, use an arbitrary safe
  value.
- clock-latency = 300 us
  Approximate worst-case latency to do a full DVFS transition for every
  OPPs. Due to the lack of HW information, use an arbitrary safe value.
  Note: The term transition-latency will be more accurate to define this
  value since the clock transition latency is not the only parameter that
  will define the overall DVFS transition.
- operating-points = < kHz - uV >
  List of 6 operating points. All of them are using the same voltage
  since the valid Vmin voltage is not documented in the HW spec.
- clocks
  phandle to the CPU clock source. This clock source is used for all the
  4 CortexA15 located inside the same cluster.
Signed-off-by: NBenoit Cousson <bcousson+renesas@baylibre.com>
[gaku.inami.xw@bp.renesas.com: Change the setting of OPPs for ES2.0]
Signed-off-by: NGaku Inami <gaku.inami.xw@bp.renesas.com>
Acked-by: NMagnus Damm <damm@opensource.se>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

The CA15 cluster is capable of voltage scaling. Add the regulator
in the i2c3 node, to allow the generic CPUFreq driver to use it.

Enable the i2c3 pin mux and the device node as well since the
da9210 is connected to that bus.

Note: In R-CAR Gen2, each frequency is using the same voltage,
and DVS control is not used. Therefore, this patch set the
voltage(Vmin/Vmax) to 1000mv.
Signed-off-by: NBenoit Cousson <bcousson@baylibre.com>
[gaku.inami.xw@bp.renesas.com: Changes Vmin for disabling DVS]
Signed-off-by: NGaku Inami <gaku.inami.xw@bp.renesas.com>
Acked-by: NMagnus Damm <damm@opensource.se>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

SCIF0 and SCIF1 are used as debug serial ports. Enable them and
configure pinmuxing appropriately. We can now remove the clkdev
registration hack for SCIF devices from the Lager reference board file.
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
[horms+renesas@verge.net.au: updated changelog to remove references to
                             device renaming]
[horms+renesas@verge.net.au: resolved conflicts]
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Acked-by: NMagnus Damm <damm@opensource.se>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

The correct binding is "micrel,led-mode", not "led-mode".

This corrects an error which was introduced when setting of ethernet PHY
LED mode was added by 82e62182d59bd1d0 ("ARM: shmobile: lager: Set ethernet
PHY LED mode").

This makes the lager code consistent with the koelsch code which was added
by ae00d12a032490b3 ("ARM: shmobile: koelsch: Set ethernet PHY LED mode").
Acked-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

The Lager board uses the ethernet PHY LED0 as a link signal connected to
the ethernet controller. Specify the corresponding LED mode for the PHY.
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Add DTS gpio-keys support for SW2 on the Lager board.
This makes the DT code match the legacy board code.
Signed-off-by: NMagnus Damm <damm@opensource.se>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Add pinctrl and SPI device for MSIOF on Lager.
On this board, only MSIOF1 is in use. Its bus contains a single device
(a Renesas R2A11302FT PMIC), for which no bindings are defined yet.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@linux-m68k.org>
Acked-by: NMagnus Damm <damm@opensource.se>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Prepare for the advent of MSIOF SPI, which will be spi1 to spi4.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@linux-m68k.org>
Acked-by: NMagnus Damm <damm@opensource.se>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Fix probable typo of renesas,groups in the lager dt. The kernel has no
renesas,gpios but this should match renesas,groups.
Signed-off-by: NRob Taylor <rob.taylor@codethink.co.uk>
[ben.dooks@codethink.co.uk: fixup description]
Signed-off-by: NBen Dooks <ben.dooks@codethink.co.uk>
Acked-by: NGeert Uytterhoeven <geert@linux-m68k.org>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Define the Lager board dependent part of the Ether device node.
Signed-off-by: NSergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

The DU device has no DT bindings yet, instantiate it as a platform
device for now.
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: NMagnus Damm <damm@opensource.se>
[horms+renesas@verge.net.au: broken out of larger patch that
                             included board changes]
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Signed-off-by: NKuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Acked-by: NMagnus Damm <damm@opensource.se>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Add pinctrl and SPI devices for QSPI on Lager.
Add Spansion s25fl512s SPI FLASH and MTD partitions.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@linux-m68k.org>
Acked-by: NMagnus Damm <damm@opensource.se>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

This enables SATA1 in Lager device tree.
SATA0 is not available on Lager since its
pinmux is fixed to USB3.0.
Signed-off-by: NValentine Barshak <valentine.barshak@cogentembedded.com>
Acked-by: NMagnus Damm <damm@opensource.se>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

The external crystal frequency is 20MHz on the Lager board. Specify it
in the device tree.
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Copy the device nodes from Lager reference into the Lager device tree
file. This will allow us to use a single DTS file regarless of kernel
configuration. In case of legacy C board code the device nodes may or
may not be used, but in the multiplatform case all the DT device nodes
are used.
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Add 2GiB of DRAM at 0x1_8000_0000 to support the full 4GiB
of Lager system memory.
Signed-off-by: NMagnus Damm <damm@opensource.se>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

In order to allow usage of the preprocessor in the SoC device tree
sources, switch from /include/ to #include.
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Now that Ether support has been added to the lager board
it is possible to use nfsroot. This configuration is
in line with that of other shmobile boards.
Acked-by: NKuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

The shmobile DT files available in the kernel are reference
implementations intended to be used as sample code, as well as for
development. As such, it makes sense to mount the root file system in
read/write mode by default.
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Lager base board support making use of 2 GiB of memory,
the r8a7790 SoC with the SCIF0 serial port and CA15 with
ARM architected timer.
Signed-off-by: NMagnus Damm <damm@opensource.se>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>