1. 25 8月, 2015 2 次提交
    • A
      perf tools: Pass Intel PT information for decoding MTC and CYC · 11fa7cb8
      Adrian Hunter 提交于
      Record additional information in the AUXTRACE_INFO event in preparation
      for decoding MTC and CYC packets.  Pass the information to the decoder.
      
      The AUXTRACE_INFO record can be extended by using the size to indicate
      the presence of new members.
      
      The additional information includes PMU config bit positions and the TSC
      to CTC (hardware crystal clock) ratio needed to decode MTC packets.
      Signed-off-by: NAdrian Hunter <adrian.hunter@intel.com>
      Cc: Jiri Olsa <jolsa@redhat.com>
      Link: http://lkml.kernel.org/r/1437150840-31811-20-git-send-email-adrian.hunter@intel.comSigned-off-by: NArnaldo Carvalho de Melo <acme@redhat.com>
      11fa7cb8
    • A
      perf tools: Add Intel PT support for PSB periods · bc9b6bf0
      Adrian Hunter 提交于
      The PSB packet is a synchronization packet that provides a starting
      point for decoding or recovery from errors.
      
      This patch adds support for a new Intel PT feature that allows the
      frequency of PSB packets to be specified.
      
      Support for this feature is indicated by
      /sys/bus/event_source/devices/intel_pt/caps/psb_cyc which contains "1"
      if the feature is supported and "0" otherwise.
      
      The PSB period can be specified as a PMU config term e.g. perf record -e
      intel_pt/psb_period=2/u sleep 1
      
      The default value is 3 or the nearest lower value that is supported.  0
      is always supported.
      
      Valid values are given by:
      
      /sys/bus/event_source/devices/intel_pt/caps/psb_periods
      
      which contains a hexadecimal value, the bits of which represent valid
      values e.g. bit 2 set means value 2 is valid.
      
      The value is converted to the approximate number of trace bytes between
      PSB packets as:
      
      	2 ^ (value + 11)
      
      e.g. value 3 means 16KiB bytes between PSBs
      
      If an invalid value is entered, the error message will give a list of
      valid values e.g.
      
      	$ perf record -e intel_pt/psb_period=15/u uname
      	Invalid psb_period for intel_pt. Valid values are: 0-5
      
      tools/perf/Documentation/intel-pt.txt is updated in a later patch as
      there are a number of new features being added.
      
      For more information about PSB periods refer to the Intel 64 and IA-32
      Architectures SDM Chapter 36 Intel Processor Trace from June 2015 or
      later.
      Signed-off-by: NAdrian Hunter <adrian.hunter@intel.com>
      Cc: Jiri Olsa <jolsa@redhat.com>
      Link: http://lkml.kernel.org/r/1437150840-31811-18-git-send-email-adrian.hunter@intel.comSigned-off-by: NArnaldo Carvalho de Melo <acme@redhat.com>
      bc9b6bf0
  2. 17 8月, 2015 1 次提交