1. 04 10月, 2006 5 次提交
    • E
      [PATCH] htirq: tidy up the htirq code · 95d77884
      Eric W. Biederman 提交于
      This moves the declarations for the architecture helpers into
      include/linux/htirq.h from the generic include/linux/pci.h.  Hopefully this
      will make this distinction clearer.
      
      htirq.h is included where it is needed.
      
      The dependency on the msi code is fixed and removed.
      
      The Makefile is tidied up.
      Signed-off-by: NEric W. Biederman <ebiederm@xmission.com>
      Cc: Ingo Molnar <mingo@elte.hu>
      Cc: Tony Luck <tony.luck@intel.com>
      Cc: Andi Kleen <ak@suse.de>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: Greg KH <greg@kroah.com>
      Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
      Signed-off-by: NAndrew Morton <akpm@osdl.org>
      Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      95d77884
    • E
      [PATCH] msi: refactor and move the msi irq_chip into the arch code · 3b7d1921
      Eric W. Biederman 提交于
      It turns out msi_ops was simply not enough to abstract the architecture
      specific details of msi.  So I have moved the resposibility of constructing
      the struct irq_chip to the architectures, and have two architecture specific
      functions arch_setup_msi_irq, and arch_teardown_msi_irq.
      
      For simple architectures those functions can do all of the work.  For
      architectures with platform dependencies they can call into the appropriate
      platform code.
      
      With this msi.c is finally free of assuming you have an apic, and this
      actually takes less code.
      
      The helpers for the architecture specific code are declared in the linux/msi.h
      to keep them separate from the msi functions used by drivers in linux/pci.h
      Signed-off-by: NEric W. Biederman <ebiederm@xmission.com>
      Cc: Ingo Molnar <mingo@elte.hu>
      Cc: Tony Luck <tony.luck@intel.com>
      Cc: Andi Kleen <ak@suse.de>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: Greg KH <greg@kroah.com>
      Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
      Signed-off-by: NAndrew Morton <akpm@osdl.org>
      Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      3b7d1921
    • E
      [PATCH] Initial generic hypertransport interrupt support · 8b955b0d
      Eric W. Biederman 提交于
      This patch implements two functions ht_create_irq and ht_destroy_irq for
      use by drivers.  Several other functions are implemented as helpers for
      arch specific irq_chip handlers.
      
      The driver for the card I tested this on isn't yet ready to be merged.
      However this code is and hypertransport irqs are in use in a few other
      places in the kernel.  Not that any of this will get merged before 2.6.19
      
      Because the ipath-ht400 is slightly out of spec this code will need to be
      generalized to work there.
      
      I think all of the powerpc uses are for a plain interrupt controller in a
      chipset so support for native hypertransport devices is a little less
      interesting.
      
      However I think this is a half way decent model on how to separate arch
      specific and generic helper code, and I think this is a functional model of
      how to get the architecture dependencies out of the msi code.
      
      [akpm@osdl.org: Kconfig fix]
      Signed-off-by: NEric W. Biederman <ebiederm@xmission.com>
      Cc: Greg KH <greg@kroah.com>
      Cc: Andi Kleen <ak@muc.de>
      Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
      Signed-off-by: NAndrew Morton <akpm@osdl.org>
      Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      8b955b0d
    • E
      [PATCH] genirq: msi: refactor the msi_ops · 38bc0361
      Eric W. Biederman 提交于
      The current msi_ops are short sighted in a number of ways, this patch attempts
      to fix the glaring deficiences.
      
      - Report in msi_ops if a 64bit address is needed in the msi message, so we
        can fail 32bit only msi structures.
      
      - Send and receive a full struct msi_msg in both setup and target.  This is
        a little cleaner and allows for architectures that need to modify the data
        to retarget the msi interrupt to a different cpu.
      
      - In target pass in the full cpu mask instead of just the first cpu in case
        we can make use of the full cpu mask.
      
      - Operate in terms of irqs and not vectors, currently there is still a 1-1
        relationship but on architectures other than ia64 I expect this will change.
      Signed-off-by: NEric W. Biederman <ebiederm@xmission.com>
      Cc: Ingo Molnar <mingo@elte.hu>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
      Cc: Rajesh Shah <rajesh.shah@intel.com>
      Cc: Andi Kleen <ak@muc.de>
      Cc: "Protasevich, Natalie" <Natalie.Protasevich@UNISYS.com>
      Cc: "Luck, Tony" <tony.luck@intel.com>
      Signed-off-by: NAndrew Morton <akpm@osdl.org>
      Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      38bc0361
    • E
      [PATCH] genirq: msi: implement helper functions read_msi_msg and write_msi_msg · 0366f8f7
      Eric W. Biederman 提交于
      In support of this I also add a struct msi_msg that captures the the two
      address and one data field ina typical msi message, and I remember the pos and
      if the address is 64bit in struct msi_desc.
      
      This makes the code a little more readable and easier to maintain, and paves
      the way to further simplfications.
      Signed-off-by: NEric W. Biederman <ebiederm@xmission.com>
      Cc: Ingo Molnar <mingo@elte.hu>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
      Cc: Rajesh Shah <rajesh.shah@intel.com>
      Cc: Andi Kleen <ak@muc.de>
      Cc: "Protasevich, Natalie" <Natalie.Protasevich@UNISYS.com>
      Cc: "Luck, Tony" <tony.luck@intel.com>
      Signed-off-by: NAndrew Morton <akpm@osdl.org>
      Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      0366f8f7
  2. 01 10月, 2006 1 次提交
    • A
      [PATCH] PCI quirks update · 236561e5
      Alan Cox 提交于
      This fixes two things
      
      Firstly someone mistakenly used "errata" for the singular.  This causes
      Dave Woodhouse to emit diagnostics whenever the string is read, and so
      should be fixed.
      
      Secondly the AMD AGP tunnel has an erratum which causes hangs if you try
      and do direct PCI to AGP transfers in some cases.  We have a flag for
      PCI/PCI failures but we need a different flag for this really as in this
      case we don't want to stop PCI/PCI transfers using things like IOAT and the
      new RAID offload work.
      
      I'll post some updates to make proper use of the PCIAGP flag in the
      media/video drivers to Mauro.
      Signed-off-by: NAlan Cox <alan@redhat.com>
      Cc: David Woodhouse <dwmw2@infradead.org>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      Signed-off-by: NAndrew Morton <akpm@osdl.org>
      Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      236561e5
  3. 27 9月, 2006 3 次提交
  4. 26 9月, 2006 3 次提交
  5. 13 7月, 2006 1 次提交
    • K
      [PATCH] PCI: PCIE power management quirk · ffadcc2f
      Kristen Carlson Accardi 提交于
      When changing power states from D0->DX and then from DX->D0, some
      Intel PCIE chipsets will cause a device reset to occur.  This will
      cause problems for any D State other than D3, since any state
      information that the driver will expect to be present coming from
      a D1 or D2 state will have been cleared.  This patch addes a
      flag to the pci_dev structure to indicate that devices should
      not use states D1 or D2, and will set that flag for the affected
      chipsets.  This patch also modifies pci_set_power_state() so that
      when a device driver tries to set the power state on
      a device that is downstream from an affected chipset, or on one
      of the affected devices it only allows state changes to or
      from D0 & D3.  In addition, this patch allows the delay time
      between D3->D0 to be changed via a quirk.  These chipsets also
      need additional time to change states beyond the normal 10ms.
      Signed-off-by: NKristen Carlson Accardi <kristen.c.accardi@intel.com>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      ffadcc2f
  6. 28 6月, 2006 1 次提交
  7. 22 6月, 2006 3 次提交
    • S
      [PATCH] PCI: disable msi mode in pci_disable_device · 99dc804d
      Shaohua Li 提交于
      Brice said the pci_save_msi_state breaks his driver in his special usage
      (not in suspend/resume), as pci_save_msi_state will disable msi mode. In
      his usage, pci_save_state will be called at runtime, and later (after
      the device operates for some time and has an error) pci_restore_state
      will be called.
      In another hand, suspend/resume needs disable msi mode, as device should
      stop working completely. This patch try to workaround this issue.
      Drivers are expected call pci_disable_device in suspend time after
      pci_save_state.
      Signed-off-by: NShaohua Li <shaohua.li@intel.com>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      99dc804d
    • D
      [PATCH] PCI Bus Parity Status-broken hardware attribute, EDAC foundation · bd8481e1
      Doug Thompson 提交于
      Currently, the EDAC (error detection and correction) modules that are in
      the kernel contain some features that need to be moved. After some good
      feedback on the PCI Parity detection code and interface
      (http://www.ussg.iu.edu/hypermail/linux/kernel/0603.1/0897.html) this
      patch ADDs an new attribute to the pci_dev structure: Namely the
      'broken_parity_status' bit.
      
      When set this indicates that the respective hardware generates false
      positives of Parity errors.
      
      The EDAC "blacklist" solution was inferior and will be removed in a
      future patch.
      
      Also in this patch is a PCI quirk.c entry for an Infiniband PCI-X card
      which generates false positive parity errors.
      
      I am requesting comments on this AND on the possibility of a exposing
      this 'broken_parity_status' bit to userland via the PCI device sysfs
      directory for devices. This access would allow for enabling of this
      feature on new devices and for old devices that have their drivers
      updated. (SLES 9 SP3 did this on an ATI motherboard video device). There
      is a need to update such a PCI attribute between kernel releases.
      
      This patch just adds a storage place for the attribute and a quirk entry
      for a known bad PCI device. PCI Parity reaper/harvestor operations are
      in EDAC itself and will be refactored to use this PCI attribute instead
      of its own mechanisms (which are currently disabled) in the future.
      Signed-off-by: NDoug Thompson <norsk5@xmission.com>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      bd8481e1
    • K
      [PATCH] PCI: Add pci_assign_resource_fixed -- allow fixed address assignments · 75acfeca
      Kumar Gala 提交于
      PCI: Add pci_assign_resource_fixed -- allow fixed address assignments
      
      On some embedded systems the PCI address for hotplug devices are not only
      known a priori but are required to be at a given PCI address for other
      master in the system to be able to access.
      
      An example of such a system would be an FPGA which is setup from user space
      after the system has booted.  The FPGA may be access by DSPs in the system
      and those DSPs expect the FPGA at a fixed PCI address.
      
      Added pci_assign_resource_fixed() as a way to allow assignment of the PCI
      devices's BARs at fixed PCI addresses.
      Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      75acfeca
  8. 24 5月, 2006 1 次提交
  9. 29 4月, 2006 1 次提交
  10. 26 4月, 2006 1 次提交
  11. 15 4月, 2006 2 次提交
  12. 24 3月, 2006 3 次提交
  13. 01 2月, 2006 1 次提交
  14. 10 1月, 2006 3 次提交
  15. 11 11月, 2005 3 次提交
    • G
    • L
      [PATCH] PCI: automatically set device_driver.owner · 863b18f4
      Laurent riffard 提交于
      A nice feature of sysfs is that it can create the symlink from the
      driver to the module that is contained in it.
      
      It requires that the device_driver.owner is set, what is not the
      case for many PCI drivers.
      
      This patch allows pci_register_driver to set automatically the
      device_driver.owner for any PCI driver.
      
      Credits to Al Viro who suggested the method.
      Signed-off-by: NLaurent Riffard <laurent.riffard@free.fr>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      --
      
       drivers/ide/setup-pci.c  |   12 +++++++-----
       drivers/pci/pci-driver.c |    9 +++++----
       include/linux/ide.h      |    3 ++-
       include/linux/pci.h      |   10 ++++++++--
       4 files changed, 22 insertions(+), 12 deletions(-)
      863b18f4
    • R
      [PATCH] PCI: add pci_find_next_capability() · 24a4e377
      Roland Dreier 提交于
      Some devices have more than one capability of the same type.  For
      example, the PCI header for the PathScale InfiniPath looks like:
      
      	04:01.0 InfiniBand: Unknown device 1fc1:000d (rev 02)
      		Subsystem: Unknown device 1fc1:000d
      		Flags: bus master, fast devsel, latency 0, IRQ 193
      		Memory at fea00000 (64-bit, non-prefetchable) [size=2M]
      		Capabilities: [c0] HyperTransport: Slave or Primary Interface
      		Capabilities: [f8] HyperTransport: Interrupt Discovery and Configuration
      
      There are _two_ HyperTransport capabilities, and the PathScale driver
      wants to look at both of them.
      
      The current pci_find_capability() API doesn't work for this, since it
      only allows us to get to the first capability of a given type.  The
      patch below introduces a new pci_find_next_capability(), which can be
      used in a loop like
      
      	for (pos = pci_find_capability(pdev, <ID>);
      	     pos;
      	     pos = pci_find_next_capability(pdev, pos, <ID>)) {
      		/* ... */
      	}
      Signed-off-by: NRoland Dreier <rolandd@cisco.com>
      Signed-off-by: NMatthew Wilcox <matthew@wil.cx>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      24a4e377
  16. 29 10月, 2005 1 次提交
    • B
      [PATCH] PCI: Block config access during BIST · e04b0ea2
      Brian King 提交于
      Some PCI adapters (eg.  ipr scsi adapters) have an exposure today in that they
      issue BIST to the adapter to reset the card.  If, during the time it takes to
      complete BIST, userspace attempts to access PCI config space, the host bus
      bridge will master abort the access since the ipr adapter does not respond on
      the PCI bus for a brief period of time when running BIST.  On PPC64 hardware,
      this master abort results in the host PCI bridge isolating that PCI device
      from the rest of the system, making the device unusable until Linux is
      rebooted.  This patch is an attempt to close that exposure by introducing some
      blocking code in the PCI code.  When blocked, writes will be humored and reads
      will return the cached value.  Ben Herrenschmidt has also mentioned that he
      plans to use this in PPC power management.
      Signed-off-by: NBrian King <brking@us.ibm.com>
      Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
      Signed-off-by: NAndrew Morton <akpm@osdl.org>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      
       drivers/pci/access.c    |   89 ++++++++++++++++++++++++++++++++++++++++++++++++
       drivers/pci/pci-sysfs.c |   20 +++++-----
       drivers/pci/pci.h       |    7 +++
       drivers/pci/proc.c      |   28 +++++++--------
       drivers/pci/syscall.c   |   14 +++----
       include/linux/pci.h     |    7 +++
       6 files changed, 134 insertions(+), 31 deletions(-)
      e04b0ea2
  17. 10 9月, 2005 4 次提交
  18. 09 9月, 2005 3 次提交