Signed-off-by: NBenjamin Gaignard <benjamin.gaignard@linaro.org>
Acked-by: NPeter Griffin <peter.griffin@linaro.org>
Signed-off-by: NHans Verkuil <hans.verkuil@cisco.com>
Signed-off-by: NMauro Carvalho Chehab <mchehab@s-opensource.com>

This patch adds the DT node for the uniperif reader
IP block found on STiH407 family silicon.
Signed-off-by: NArnaud Pouliquen <arnaud.pouliquen@st.com>
Signed-off-by: NPeter Griffin <peter.griffin@linaro.org>

This patch adds the DT nodes for the uniperif player
IP blocks found on STiH407 family silicon.
Signed-off-by: NArnaud Pouliquen <arnaud.pouliquen@st.com>
Signed-off-by: NPeter Griffin <peter.griffin@linaro.org>

This patch adds the dt node for the internal audio
codec IP.
Signed-off-by: NArnaud Pouliquen <arnaud.pouliquen@st.com>
Signed-off-by: NPeter Griffin <peter.griffin@linaro.org>

These nodes are required to get the fdma driver working
on STiH407 based silicon.
Signed-off-by: NPeter Griffin <peter.griffin@linaro.org>
Acked-by: NLee Jones <lee.jones@linaro.org>

The STiH4{07,10} platform contains some interconnect clocks which are used
by various IPs.  If these clocks aren't handled correctly by ST's SDHCI
driver MMC will break and the following output can be observed:

[   13.916949] mmc0: Timeout waiting for hardware interrupt.
[   13.922349] sdhci: =========== REGISTER DUMP (mmc0)===========
[   13.928175] sdhci: Sys addr: 0x00000000 | Version:  0x00001002
[   13.933999] sdhci: Blk size: 0x00007040 | Blk cnt:  0x00000001
[   13.939825] sdhci: Argument: 0x00fffff0 | Trn mode: 0x00000013
[   13.945650] sdhci: Present:  0x1fff0206 | Host ctl: 0x00000011
[   13.951475] sdhci: Power:    0x0000000f | Blk gap:  0x00000080
[   13.957300] sdhci: Wake-up:  0x00000000 | Clock:    0x00003f07
[   13.963126] sdhci: Timeout:  0x00000004 | Int stat: 0x00000000
[   13.968952] sdhci: Int enab: 0x02ff008b | Sig enab: 0x02ff008b
[   13.974777] sdhci: AC12 err: 0x00000000 | Slot int: 0x00000000
[   13.980602] sdhci: Caps:     0x21ed3281 | Caps_1:   0x00000000
[   13.986428] sdhci: Cmd:      0x0000063a | Max curr: 0x00000000
[   13.992252] sdhci: Host ctl2: 0x00000000
[   13.996166] sdhci: ADMA Err: 0x00000000 | ADMA Ptr: 0x7c048200
[   14.001990] sdhci: ===========================================
[   14.009802] mmc0: Got data interrupt 0x02000000 even though no data operation was in progress.

Cc: stable@vger.kernel.org
Tested-by: NPeter Griffin <peter.griffin@linaro.org>
Signed-off-by: NLee Jones <lee.jones@linaro.org>
Acked-by: NPatrice Chotard <patrice.chotard@st.com>

Signed-off-by: NLee Jones <lee.jones@linaro.org>

Despite ST AHCI version = 1.3, reading HOST_PORTS_IMPL
returns 0. So force HOST_PORTS_IMPL to 1 by using
ports-implemented DT property.
Signed-off-by: NPatrice Chotard <patrice.chotard@st.com>
Signed-off-by: NLee Jones <lee.jones@linaro.org>
Reviewed-by: NPeter Griffin <peter.griffin@linaro.org>

Due to 96board which uses mmc0 node for SD card, the non-removable
property must be moved from STiH407-family to board file for B2120
and B2199 boards.
Signed-off-by: NPatrice Chotard <patrice.chotard@st.com>
Signed-off-by: NLee Jones <lee.jones@linaro.org>
Reviewed-by: NPeter Griffin <peter.griffin@linaro.org>

Despite ST AHCI version = 1.3, reading HOST_PORTS_IMPL
returns 0. So force HOST_PORTS_IMPL to 1 by using
ports-implemented DT property.
Signed-off-by: NPatrice Chotard <patrice.chotard@st.com>
Signed-off-by: NTejun Heo <tj@kernel.org>

This patch fixes a non-booting issue in Mainline.

When booting with a compressed kernel, we need to be careful how we
populate memory close to DDR start.  AUTO_ZRELADDR is enabled by default
in multi-arch enabled configurations, which place some restrictions on
where the kernel is placed and where it will be uncompressed to on boot.

AUTO_ZRELADDR takes the decompressor code's start address and masks out
the bottom 28 bits to obtain an address to uncompress the kernel to
(thus a load address of 0x42000000 means that the kernel will be
uncompressed to 0x40000000 i.e. DDR START on this platform).

Even changing the load address to after the co-processor's shared memory
won't render a booting platform, since the AUTO_ZRELADDR algorithm still
ensures the kernel is uncompressed into memory shared with the first
co-processor (0x40000000).

Another option would be to move loading to 0x4A000000, since this will
mean the decompressor will decompress the kernel to 0x48000000. However,
this would mean a large chunk (0x44000000 => 0x48000000 (64MB)) of
memory would essentially be wasted for no good reason.

Until we can work with ST to find a suitable memory location to
relocate co-processor shared memory, let's disable the shared memory
nodes.  This will ensure a working platform in the mean time.

NB: The more observant of you will notice that we're leaving the DMU
shared memory node enabled; this is because a) it is the only one in
active use at the time of this writing and b) it is not affected by
the current default behaviour which is causing issues.

Fixes: fe135c63 (ARM: dts: STiH407: Move over to using the 'reserved-memory' API for obtaining DMA memory)
Signed-off-by: NLee Jones <lee.jones@linaro.org>
Reviewed-by Peter Griffin <peter.griffin@linaro.org>
Signed-off-by: NMaxime Coquelin <maxime.coquelin@st.com>
Signed-off-by: NOlof Johansson <olof@lixom.net>

This aligns with the internal configuration.
Signed-off-by: NLee Jones <lee.jones@linaro.org>
Signed-off-by: NMaxime Coquelin <maxime.coquelin@st.com>

Doing so saves quite a bit of code in the driver.

For more information on the 'reserved-memory' bindings see:

  Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
Suggested-by: NSuman Anna <s-anna@ti.com>
Signed-off-by: NLee Jones <lee.jones@linaro.org>
Signed-off-by: NMaxime Coquelin <maxime.coquelin@st.com>

Signed-off-by: NLudovic Barre <ludovic.barre@st.com>
Signed-off-by: NLee Jones <lee.jones@linaro.org>
Signed-off-by: NMaxime Coquelin <maxime.coquelin@st.com>

This patch supplies the Mailbox Controller nodes.  In order to
request channels, these nodes will be referenced by Mailbox
Client nodes.
Signed-off-by: NLee Jones <lee.jones@linaro.org>
Signed-off-by: NMaxime Coquelin <maxime.coquelin@st.com>

This is used for CPU Frequency Scaling.
Signed-off-by: NLee Jones <lee.jones@linaro.org>
Signed-off-by: NMaxime Coquelin <maxime.coquelin@st.com>

Used for Voltage Scaling using CPUFreq.
Signed-off-by: NLee Jones <lee.jones@linaro.org>
Signed-off-by: NMaxime Coquelin <maxime.coquelin@st.com>

Signed-off-by: NLee Jones <lee.jones@linaro.org>
Signed-off-by: NMaxime Coquelin <maxime.coquelin@st.com>

You'll notice that the voltage cell is populated with 0's.  Voltage
information is very platform specific, even depends on 'cut' and
'substrate' versions.  Thus it is left blank for a generic (safe)
implementation.  If other nodes/properties are provided by the
bootloader, the ST CPUFreq driver will over-ride these generic
values.
Signed-off-by: NLee Jones <lee.jones@linaro.org>
Signed-off-by: NMaxime Coquelin <maxime.coquelin@st.com>

STiH407 family uses the Synopsys IP.
Signed-off-by: NMaxime Coquelin <maxime.coquelin@st.com>

Signed-off-by: NLee Jones <lee.jones@linaro.org>
Signed-off-by: NMaxime Coquelin <maxime.coquelin@st.com>

Now we have default pinconfig groups for each SPI
controller ensure it is used by the SPI controller
node.
Acked-by: NLee Jones <lee.jones@linaro.org>
Acked-by: NPatrice Chotard <patrice.chotard@st.com>
Signed-off-by: NPeter Griffin <peter.griffin@linaro.org>
Signed-off-by: NMaxime Coquelin <maxime.coquelin@st.com>

The display nodes are common to both STiH407 and STiH410, move them to the
family file.
Acked-by: NPatrice Chotard <patrice.chotard@st.com>
Acked-by: NPeter Griffin <peter.griffin@linaro.org>
Signed-off-by: NMaxime Coquelin <maxime.coquelin@st.com>

The PWM may not be used on some boards, so enable them only the board file.
Acked-by: NPatrice Chotard <patrice.chotard@st.com>
Acked-by: NPeter Griffin <peter.griffin@linaro.org>
Signed-off-by: NMaxime Coquelin <maxime.coquelin@st.com>

Signed-off-by: NLee Jones <lee.jones@linaro.org>
Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>

By popular vote, the DT binding includes for reset controllers are located
in include/dt-bindings/reset/. Move the STi reset constants in there, too,
to avoid confusion.
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>
Acked-by: NPatrice Chotard <patrice.chotard@st.com>

Signed-off-by: NLee Jones <lee.jones@linaro.org>
Signed-off-by: NMaxime Coquelin <maxime.coquelin@st.com>

This also incorporates the STiH410.
Signed-off-by: NLee Jones <lee.jones@linaro.org>
Signed-off-by: NMaxime Coquelin <maxime.coquelin@st.com>

To enable SMP when booting via u-boot we need to specify the
newly implemented cpu-release-addr DT property.
Signed-off-by: NPeter Griffin <peter.griffin@linaro.org>
Acked-by: NMaxime Coquelin <maxime.coquelin@st.com>
Signed-off-by: NMaxime Coquelin <maxime.coquelin@st.com>

This driver is used to enable System Configuration Register controlled
External, CTI (Core Sight), PMU (Performance Management), and PL310 L2
Cache IRQs prior to use.

Here we are enabling PMU IRQs on both channels.
Signed-off-by: NLee Jones <lee.jones@linaro.org>
Signed-off-by: NMaxime Coquelin <maxime.coquelin@st.com>

This is ARM's generic Performance Monitoring Unit.
Signed-off-by: NLee Jones <lee.jones@linaro.org>
Signed-off-by: NMaxime Coquelin <maxime.coquelin@st.com>

Signed-off-by: NLee Jones <lee.jones@linaro.org>
Signed-off-by: NMaxime Coquelin <maxime.coquelin@st.com>

Now that both usb2 and usb3 phy drivers, and also the ST dwc3 glue code
are all present upstream, we can add the dwc3 DT node and have a working
usb3 controller on stih407-b2120 and stih410-b2020.
Signed-off-by: NPeter Griffin <peter.griffin@linaro.org>
Acked-by: NLee Jones <lee.jones@linaro.org>
Acked-by: NMaxime Coquelin <maxime.coquelin@st.com>
Signed-off-by: NMaxime Coquelin <maxime.coquelin@st.com>

Ths picophyreset is incorrectly defined, which stops the usb2 phy being
taken out of reset.
Signed-off-by: NPeter Griffin <peter.griffin@linaro.org>
Acked-by: NLee Jones <lee.jones@linaro.org>
Signed-off-by: NMaxime Coquelin <maxime.coquelin@st.com>

Now that the miphy28lp is upstream, we can add the sata dt nodes
for stih407 family silicon. This has been tested on b2120 board
J4 (sata0 channel). These nodes are disabled by default as a
special mini pci-e to sata daughter board is required which
isn't shipped with the board.
Signed-off-by: NPeter Griffin <peter.griffin@linaro.org>
Acked-by: NLee Jones <lee.jones@linaro.org>
Acked-by: NMaxime Coquelin <maxime.coquelin@st.com>
Signed-off-by: NMaxime Coquelin <maxime.coquelin@st.com>

On current ST platforms the LPC controls a number of functions.  This
patch enables support for the LPC Watchdog and LPC RTC devices on LPC1
and LPC2 respectively.
Signed-off-by: NDavid Paris <david.paris@st.com>
Signed-off-by: NLee Jones <lee.jones@linaro.org>
Signed-off-by: NMaxime Coquelin <maxime.coquelin@st.com>

The nodes have been split to allow as much commonality as possible.
The stih407 has a silicon bug with eMMC UHS modes (with top regs)
and as such doesn't have any of the uhs dt properties.
Signed-off-by: NPeter Griffin <peter.griffin@linaro.org>
Signed-off-by: NMaxime Coquelin <maxime.coquelin@st.com>

The Synchronous Serial Controller is used to provide SPI.

These are the ports which are located on the Stand-By Controller (SBC).
Signed-off-by: NLee Jones <lee.jones@linaro.org>
Signed-off-by: NMaxime Coquelin <maxime.coquelin@st.com>

The Synchronous Serial Controller is used to provide SPI.
Signed-off-by: NLee Jones <lee.jones@linaro.org>
Signed-off-by: NMaxime Coquelin <maxime.coquelin@st.com>

The MiPHY28lp is a Generic PHY which can serve various SATA, PCIe or
USB3 devices. The two first ports can be use for either; both SATA, both
PCIe or one of each in any configuration.
The Third port is only for USB3.
Signed-off-by: NGabriel Fernandez <gabriel.fernandez@linaro.org>
Signed-off-by: NMaxime Coquelin <maxime.coquelin@st.com>