1. 14 9月, 2012 1 次提交
  2. 12 5月, 2012 1 次提交
    • S
      ARM: msm: Drop useless teq from DEBUG_LL support · c97d9320
      Stephen Boyd 提交于
      This teq was first introduced in bcc0f6af ([ARM] msm: clean up
      iomap and devices, 2008-09-10). It seems that DEBUG_LL support on
      MSM at the time had to remove the virtual mapping for the uart
      base. Thus when the MMU was enabled the addruart macro returned 0
      and the senduart macro would test for 0 and do nothing. It was a
      simple way to turn off DEBUG_LL when the MMU was enabled.
      
      The virtual mapping was added back in 6339f669 (msm: make
      debugging UART (for DEBUG_LL) configurable, 2009-11-02) but the
      patch forgot to remove the teq here. So as it stands the teq has
      been useless for two years and DEBUG_LL works fine without it.
      
      Cc: Nicolas Pitre <nico@fluxnic.net>
      Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
      Signed-off-by: NDavid Brown <davidb@codeaurora.org>
      c97d9320
  3. 08 5月, 2012 1 次提交
  4. 03 4月, 2012 1 次提交
  5. 14 3月, 2012 1 次提交
  6. 07 3月, 2012 3 次提交
  7. 22 2月, 2012 1 次提交
  8. 21 1月, 2012 2 次提交
  9. 05 1月, 2012 2 次提交
  10. 27 11月, 2011 1 次提交
  11. 16 11月, 2011 1 次提交
  12. 11 11月, 2011 2 次提交
  13. 27 10月, 2011 1 次提交
  14. 23 10月, 2011 1 次提交
    • M
      ARM: gic: consolidate PPI handling · 292b293c
      Marc Zyngier 提交于
      PPI handling is a bit of an odd beast. It uses its own low level
      handling code and is hardwired to the local timers (hence lacking
      a registration interface).
      
      Instead, switch the low handling to the normal SPI handling code.
      PPIs are handled by the handle_percpu_devid_irq flow.
      
      This also allows the removal of some duplicated code.
      
      Cc: Kukjin Kim <kgene.kim@samsung.com>
      Cc: David Brown <davidb@codeaurora.org>
      Cc: Bryan Huntsman <bryanh@codeaurora.org>
      Cc: Tony Lindgren <tony@atomide.com>
      Cc: Paul Mundt <lethal@linux-sh.org>
      Cc: Magnus Damm <magnus.damm@gmail.com>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Acked-by: NDavid Brown <davidb@codeaurora.org>
      Tested-by: NDavid Brown <davidb@codeaurora.org>
      Tested-by: NShawn Guo <shawn.guo@linaro.org>
      Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>
      292b293c
  15. 14 10月, 2011 1 次提交
  16. 26 9月, 2011 1 次提交
  17. 13 8月, 2011 1 次提交
    • S
      ARM: 7012/1: Set proper TEXT_OFFSET for newer MSMs · 9e775ad1
      Stephen Boyd 提交于
      MSMs post 8x50 have 2Mb at the beginning of RAM reserved for
      shared memory. Since the kernel hasn't typically been told this
      RAM exists, PHYS_OFFSET has been set to 0xN0200000 and the memory
      atags passed to the kernel have matched. This doesn't play nicely
      with things such as AUTO_ZRELADDR, which doesn't work at all, and
      dynamic phys to virt, which requires an MSM specific workaround.
      
      Work around these issues by telling the kernel RAM starts at
      0xN0000000 (it actually does) and fixup the atags from the
      bootloader (if necessary) to say the same. In addition, make sure
      to set TEXT_OFFSET at least 2Mb beyond the start of RAM so that
      the kernel doesn't end up being decompressed into shared memory.
      
      After doing this, AUTO_ZRELADDR should work on MSM with no
      problems and ARM_PATCH_PHYS_VIRT_16BIT should no longer be
      necessary.
      Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
      Acked-by: NNicolas Pitre <nicolas.pitre@linaro.org>
      Acked-by: NDavid Brown <davidb@codeaurora.org>
      Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      9e775ad1
  18. 12 8月, 2011 3 次提交
  19. 01 8月, 2011 2 次提交
  20. 20 7月, 2011 1 次提交
  21. 23 5月, 2011 1 次提交
  22. 10 5月, 2011 1 次提交
  23. 09 3月, 2011 5 次提交
  24. 01 3月, 2011 2 次提交
  25. 18 2月, 2011 1 次提交
  26. 15 2月, 2011 1 次提交
  27. 29 1月, 2011 1 次提交