- 02 6月, 2016 3 次提交
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由 Krzysztof Kozlowski 提交于
The exynos5250_clk_sleep_init() function can be moved to init section because it is referenced only from other init-level calls. Signed-off-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
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由 Krzysztof Kozlowski 提交于
All of initialization data can be made const. Signed-off-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
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由 Krzysztof Kozlowski 提交于
The samsung_clk_init() cannot return NULL. Either it returns allocated memory or it panics. Signed-off-by: NKrzysztof Kozlowski <krzk@kernel.org> Reviewed-by: NJavier Martinez Canillas <javier@osg.samsung.com> Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
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- 03 3月, 2016 1 次提交
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由 Stephen Boyd 提交于
This flag is a no-op now. Remove usage of the flag. Acked-by: NSylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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- 24 10月, 2015 1 次提交
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由 Tomeu Vizoso 提交于
When the DISP1 power domain is powered off, there's two clocks that need to be temporarily reparented to OSC, and back to their original parents when the domain is powered on again. We expose these two clocks in the DT bindings so that the DT node of the power domain can reference them. Signed-off-by: NTomeu Vizoso <tomeu.vizoso@collabora.com> Acked-by: NStephen Boyd <sboyd@codeaurora.org> Signed-off-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: NKukjin Kim <kgene@kernel.org>
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- 24 7月, 2015 1 次提交
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由 Thomas Abraham 提交于
With the addition of the new Samsung specific cpu-clock type, the arm clock can be represented as a cpu-clock type. Add the CPU clock configuration data and instantiate the CPU clock type for Exynos5250. Cc: Tomasz Figa <tomasz.figa@gmail.com> Signed-off-by: NThomas Abraham <thomas.ab@samsung.com> [b.zolnierkie: split exynos5250 support from the original patch] [b.zolnierkie: moved E5250_CPU_DIV[0,1] macros to clk-exynos5250.c] Signed-off-by: NBartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Reviewed-by: NJavier Martinez Canillas <javier@dowhile0.org> Tested-by: NJavier Martinez Canillas <javier@dowhile0.org> Acked-by: NSylwester Nawrocki <s.nawrocki@samsung.com> Acked-by: NViresh Kumar <viresh.kumar@linaro.org> Signed-off-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com> Acked-by: NMichael Turquette <mturquette@baylibre.com> Signed-off-by: NKukjin Kim <kgene@kernel.org>
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- 21 7月, 2015 1 次提交
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由 Stephen Boyd 提交于
Clock provider drivers generally shouldn't include clk.h because it's the consumer API. Only include clk.h in files that are using it. The clkdev.h header isn't always used either, so remove it and add in slab.h where files were relying on it to include slab for them. Cc: Chanwoo Choi <cw00.choi@samsung.com> Cc: Sylwester Nawrocki <s.nawrocki@samsung.com> Cc: Krzysztof Kozlowski <k.kozlowski@samsung.com> Cc: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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- 26 7月, 2014 1 次提交
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由 Krzysztof Kozlowski 提交于
Array of struct of_device_id may be be const as expected by of_match_table field and of_find_matching_node_and_match() function. Signed-off-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com> Reviewed-by: NJingoo Han <jg1.han@samsung.com> Signed-off-by: NTomasz Figa <t.figa@samsung.com>
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- 30 6月, 2014 2 次提交
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由 Sylwester Nawrocki 提交于
Ensure the clock provider is not registered until after all its related clocks were created and are ready to use. Currently there are races possible and any (of_)clk_get() call right after a clock provider's clk_init_cb callback call may fail. Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: NTomasz Figa <t.figa@samsung.com>
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由 Rahul Sharma 提交于
Change bit from 2 to 9 for tv (mixer) sysmmu clock. Signed-off-by: NRahul Sharma <rahul.sharma@samsung.com> Reviewed-by: NSachin Kamat <sachin.kamat@samsung.com> Acked-by: NKukjin Kim <kgene.kim@samsung.com> Signed-off-by: NTomasz Figa <t.figa@samsung.com>
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- 26 5月, 2014 2 次提交
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由 Cho KyongHo 提交于
This patch adds the missing sysmmu clocks for Display and ISP blocks. Signed-off-by: NCho KyongHo <pullip.cho@samsung.com> Signed-off-by: NShaik Ameer Basha <shaik.ameer@samsung.com> Acked-by: NTomasz Figa <t.figa@samsung.com> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
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由 Amit Daniel Kachhap 提交于
Now with common clock support added for exynos5250 it is necessary to move this code to exynos5250 common clock driver as clock registers should be handled there. This change is tested in exynos5250 based arndale platform. Cc: Abhilash Kesavan <a.kesavan@samsung.com> Cc: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: NKukjin Kim <kgene.kim@samsugn.com> Reviewed-by: NBartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Signed-off-by: NAmit Daniel Kachhap <amit.daniel@samsung.com> [t.figa: Rebased onto current kernel sources.] Signed-off-by: NTomasz Figa <t.figa@samsung.com> Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
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- 15 5月, 2014 3 次提交
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由 Arun Kumar K 提交于
This patch adds the required clocks for ARM Mali IP in Exynos5250. Signed-off-by: NArun Kumar K <arun.kk@samsung.com> [t.figa: Changed clock ID to avoid conflict with CLK_SSS] Signed-off-by: NTomasz Figa <t.figa@samsung.com>
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由 Naveen Krishna Chatradhi 提交于
This patch adds gating clock for SSS(Security SubSystem) module on Exynos5250/5420. Signed-off-by: NNaveen Krishna Chatradhi <ch.naveen@samsung.com> [t.figa: Fixed sort order and group name.] Signed-off-by: NTomasz Figa <t.figa@samsung.com>
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由 Rahul Sharma 提交于
Samsung CCF helper functions do not provide support to register multiple Clock Providers for a given SoC. Due to this limitation, SoC platforms are not able to use these helpers for registering multiple clock providers and are forced to bypass this layer. This layer is modified accordingly to enable the support for multiple clock providers. Clock file for exynos4, exynos5250, exynos5420, exynos5440, S3c64xx, S3c24xx are also modified as per changed helper functions. Signed-off-by: NRahul Sharma <rahul.sharma@samsung.com> [t.figa: Modified s3c2410 clock driver as well] Signed-off-by: NTomasz Figa <t.figa@samsung.com>
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- 14 2月, 2014 2 次提交
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由 Tomasz Figa 提交于
Since all SoC drivers have been moved to local suspend/resume handling, the old code can be safely dropped. Signed-off-by: NTomasz Figa <t.figa@samsung.com> Acked-by: NKyungmin Park <kyungmin.park@samsung.com> Acked-by: NHeiko Stuebner <heiko@sntech.de> Reviewed-by: NThomas Abraham <thomas.ab@samsung.com> Reviewed-by: NSylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
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由 Tomasz Figa 提交于
Since there are multiple differences in how suspend/resume of particular Exynos SoCs must be handled, SoC driver is better place for suspend/resume handlers and so this patch moves them. Signed-off-by: NTomasz Figa <t.figa@samsung.com> Acked-by: NKyungmin Park <kyungmin.park@samsung.com> Reviewed-by: NThomas Abraham <thomas.ab@samsung.com> Reviewed-by: NSylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
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- 09 1月, 2014 3 次提交
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由 Andrew Bresticker 提交于
There is no gate for the PCM clock input to the AudioSS block, so the parent of sclk_pcm is div_pcm0. Add a clock ID for it so that we can reference it in device trees. Signed-off-by: NAndrew Bresticker <abrestic@chromium.org> Reviewed-by: NTomasz Figa <t.figa@samsung.com> Acked-by: NMike Turquette <mturquette@linaro.org> Acked-by: NKukjin Kim <kgene.kim@samsung.com> Signed-off-by: NTomasz Figa <t.figa@samsung.com>
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由 Andrzej Hajda 提交于
The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: NAndrzej Hajda <a.hajda@samsung.com> Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com> Acked-by: NMike Turquette <mturquette@linaro.org> Acked-by: NKukjin Kim <kgene.kim@samsung.com> Signed-off-by: NTomasz Figa <t.figa@samsung.com>
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由 Andrew Bresticker 提交于
Register the APLL rate table so that we can set the APLL rate from the cpufreq driver. Signed-off-by: NAndrew Bresticker <abrestic@chromium.org> Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org> Signed-off-by: NTomasz Figa <t.figa@samsung.com>
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- 31 12月, 2013 12 次提交
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由 Sachin Kamat 提交于
Add CLK_SET_RATE_PARENT flag to mout_apll clock. This will let us set the clock rate in the cpufreq driver. Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org> Acked-by: NMike Turquette <mturquette@linaro.org> Signed-off-by: NTomasz Figa <t.figa@samsung.com>
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由 Tomasz Figa 提交于
This patch adds mout_aclk333_sub mux clock and updates gate clocks from MFC domain to have it as their parent as specified in SoC documentation. Signed-off-by: NTomasz Figa <t.figa@samsung.com> Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com> Tested-by: NTomasz Figa <t.figa@samsung.com>
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由 Tomasz Figa 提交于
According to SoC documentation, input 5 of mout_audio muxes is connected to xxti (named fin_pll in the driver). This patch corrects defined parent arrays to match SoC documentation. Signed-off-by: NTomasz Figa <t.figa@samsung.com> Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com> Tested-by: NTomasz Figa <t.figa@samsung.com>
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由 Tomasz Figa 提交于
This patch updates mux parent arrays with unpopulated mux inputs, as all inputs need to be specified in parent arrays passed to clk_register_mux(), otherwise clk_set_parent() can generate out of bound accesses to the array. Signed-off-by: NTomasz Figa <t.figa@samsung.com> Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com> Tested-by: NTomasz Figa <t.figa@samsung.com>
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由 Tomasz Figa 提交于
This patch adds mux_aclk_200_disp1_sub mux clock, which according to SoC documentation is the correct parent of DISP1 gate clocks. Signed-off-by: NTomasz Figa <t.figa@samsung.com> Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com> Tested-by: NTomasz Figa <t.figa@samsung.com>
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由 Tomasz Figa 提交于
This patch adds mout_aclk266_gscl_sub mux clock and adjusts definitions of GSCL domain gate clocks to use it as their parent, as specified in SoC documentation. Signed-off-by: NTomasz Figa <t.figa@samsung.com> Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com> Tested-by: NTomasz Figa <t.figa@samsung.com>
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由 Tomasz Figa 提交于
This patch renames all mux clocks to start with mout_ prefix and all div clocks to start with div_ prefix for consistency with other clocks already defined this way. Signed-off-by: NTomasz Figa <t.figa@samsung.com> Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com> Tested-by: NTomasz Figa <t.figa@samsung.com>
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由 Tomasz Figa 提交于
This patch reorders clock definitions, so they are sorted by register addresses and bitfield shifts. When at it, blank lines are added to separate definitions of clocks from different registers. Overall this should make the driver more readable and reduce the number of potential conflicts when adding new entries. Signed-off-by: NTomasz Figa <t.figa@samsung.com> Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com> Tested-by: NTomasz Figa <t.figa@samsung.com>
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由 Abhilash Kesavan 提交于
The sysreg (system register) generates control signals for various blocks like disp1blk, i2c, mipi, usb etc. However, it gets disabled as an unused clock at boot-up. This can lead to failures in operation of above blocks, because they can not be configured properly if this clock is disabled. Signed-off-by: NAbhilash Kesavan <a.kesavan@samsung.com> Acked-by: NMike Turquette <mturquette@linaro.org> [t.figa: Updated patch description.] Signed-off-by: NTomasz Figa <t.figa@samsung.com>
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由 Abhilash Kesavan 提交于
Adds gate clock for MDMA0 on Exynos5250 SoC. This is needed to ensure that the clock is enabled when MDMA0 is used on systems on which firmware gates the clockby default. Signed-off-by: NAbhilash Kesavan <a.kesavan@samsung.com> Acked-by: NMike Turquette <mturquette@linaro.org> [t.figa: Updated patch description.] Signed-off-by: NTomasz Figa <t.figa@samsung.com>
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由 Abhilash Kesavan 提交于
The CLK_GATE_IP_ACP register offset is incorrectly listed making definition of g2d clock incorrect, which may lead to system failures when trying to use G2D on systems on which firmware gates this clock by default. Fix this and the register ordering as well. Signed-off-by: NAbhilash Kesavan <a.kesavan@samsung.com> Acked-by: NMike Turquette <mturquette@linaro.org> [t.figa: Updated patch description.] Signed-off-by: NTomasz Figa <t.figa@samsung.com>
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由 Andrew Bresticker 提交于
The gate clocks for the MFC sysmmus appear to be flipped, i.e. GATE_IP_MFC[2] gates sysmmu_mfcl and GATE_IP_MFC[1] gates sysmmu_mfcr. Fix this so that the MFC will start up. Signed-off-by: NAndrew Bresticker <abrestic@chromium.org> Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org> Acked-by: NMike Turquette <mturquette@linaro.org> Signed-off-by: NTomasz Figa <t.figa@samsung.com>
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- 07 9月, 2013 1 次提交
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由 Tomasz Figa 提交于
Since the _get_rate() helper has been modified to use __clk_lookup() internally, checking of PLL input rates can be done using it and so the registration code can be simplified. Signed-off-by: NTomasz Figa <t.figa@samsung.com> Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com> Reviewed-by: NSylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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- 29 8月, 2013 1 次提交
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由 Rahul Sharma 提交于
parent of hdmi and mixer block is mentioned as aclk200 which is not correct. It is clocked by the ouput of aclk200_disp1. Hence parent for mixer and hdmi clocks is changed to aclk200_disp1. Signed-off-by: NRahul Sharma <rahul.sharma@samsung.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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- 09 8月, 2013 2 次提交
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由 Sachin Kamat 提交于
__initdata should be placed between the variable name and equal sign for the variable to be placed in the intended section. Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Sachin Kamat 提交于
exynos5250_plls is used only in this file. Make it static. Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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- 03 8月, 2013 4 次提交
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由 Vikas Sajjan 提交于
Adds the EPLL and VPLL freq table for exynos5250 SoC. Signed-off-by: NVikas Sajjan <vikas.sajjan@linaro.org> Signed-off-by: NYadwinder Singh Brar <yadi.brar@samsung.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Vikas Sajjan 提交于
While trying to get rate of "mout_vpllsrc" MUX (parent) for registering the "fout_vpll" (child), we found get rate was failing. So this patch moves the mout_vpllsrc MUX out of the existing common list and registers the mout_vpllsrc MUX before the PLL registrations. Reviewed-by: NTomasz Figa <t.figa@samsung.com> Signed-off-by: NVikas Sajjan <vikas.sajjan@linaro.org> Signed-off-by: NYadwinder Singh Brar <yadi.brar@samsung.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Yadwinder Singh Brar 提交于
This patch defines a common rate_table which will contain recommended p, m, s, k values for supported rates that needs to be changed for changing corresponding PLL's rate. Reviewed-by: NDoug Anderson <dianders@chromium.org> Signed-off-by: NYadwinder Singh Brar <yadi.brar@samsung.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Yadwinder Singh Brar 提交于
This patch migrates exynos5250 pll registeration to use common samsung_clk_register_pll() by intialising table of PLLs and adding PLLs to unique id list of clocks. Signed-off-by: NYadwinder Singh Brar <yadi.brar@samsung.com> Signed-off-by: NVikas Sajjan <vikas.sajjan@linaro.org> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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