- 16 7月, 2016 1 次提交
-
-
由 Michael Turquette 提交于
This reverts commit e16fb2e6. Updated documentation from the chip vendor reveals that this clock is not required for correct operation of the MMC controller. As such, do not expose it to DT. Signed-off-by: NMichael Turquette <mturquette@baylibre.com>
-
- 08 7月, 2016 1 次提交
-
-
由 Kevin Hilman 提交于
The MMC_PCLK is needed for the SD/eMMC driver, expose to DT (and comment out in clk driver) Signed-off-by: NKevin Hilman <khilman@baylibre.com> Signed-off-by: NMichael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/20160707033837.20029-1-khilman@baylibre.com
-
- 07 7月, 2016 2 次提交
-
-
由 Paul Gortmaker 提交于
The Kconfig currently controlling compilation of this code is: drivers/clk/meson/Kconfig:config COMMON_CLK_GXBB drivers/clk/meson/Kconfig: bool ...meaning that it currently is not being built as a module by anyone. Lets remove the modular code that is essentially orphaned, so that when reading the driver there is no doubt it is builtin-only. Since module_init translates to device_initcall in the non-modular case, the init ordering remains unchanged with this commit. Also note that MODULE_DEVICE_TABLE and ALIAS are no-op for non-modules. We also delete the MODULE_LICENSE tag etc. since all that information was (or is now) contained at the top of the file in the comments. Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Carlo Caione <carlo@caione.org> Cc: Kevin Hilman <khilman@baylibre.com> Cc: linux-clk@vger.kernel.org Cc: linux-amlogic@lists.infradead.org Signed-off-by: NPaul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: NMichael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/20160704211220.5685-3-paul.gortmaker@windriver.com
-
由 Paul Gortmaker 提交于
The Kconfig currently controlling compilation of this code is: drivers/clk/meson/Kconfig:config COMMON_CLK_MESON8B drivers/clk/meson/Kconfig: bool ...meaning that it currently is not being built as a module by anyone. However a recent commit added a bunch of modular boilerplate to this driver. Lets remove the modular code that is essentially orphaned, so that when reading the driver there is no doubt it is builtin-only. Since module_init translates to device_initcall in the non-modular case, the init ordering remains unchanged with this commit. Also note that MODULE DEVICE_TABLE/ALIAS are no-op when non-modular. We also delete the MODULE_LICENSE tag etc. since all that information was (or is now) contained at the top of the file in the comments. Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Carlo Caione <carlo@caione.org> Cc: Kevin Hilman <khilman@baylibre.com> Cc: linux-clk@vger.kernel.org Cc: linux-amlogic@lists.infradead.org Signed-off-by: NPaul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: NMichael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/20160704211220.5685-2-paul.gortmaker@windriver.com
-
- 23 6月, 2016 13 次提交
-
-
由 Michael Turquette 提交于
The gxbb clock controller is the primary clock generation unit for the AmLogic GXBB SoC. It is clocked by a fixed 24MHz xtal, contains several PLLs and the usual post-dividers, muxes, dividers and leaf gates that are fed into various IP blocks in the SoC. Tested-by: NKevin Hilman <khilman@baylibre.com> Signed-off-by: NMichael Turquette <mturquette@baylibre.com>
-
由 Michael Turquette 提交于
Fractional MPLLs are a superset of the existing AmLogic MPLLs. They add in a couple of new bitfields for further dividing the clock rate to achieve rates with fractional hertz. Tested-by: NKevin Hilman <khilman@baylibre.com> Signed-off-by: NMichael Turquette <mturquette@baylibre.com>
-
由 Michael Turquette 提交于
MPLLs are adjustable rate clocks derived from PLLs. On both Meson8b and GXBB they appear to be only derived from fixed_pll. Add support for these clock types so that they can be added to their respective drivers. Tested-by: NKevin Hilman <khilman@baylibre.com> Signed-off-by: NMichael Turquette <mturquette@baylibre.com>
-
由 Michael Turquette 提交于
There are a series of peripheral and system gate clocks that fan out from the clk81 signal. Add a helper macro to statically initialize these gate clocks. Tested-by: NKevin Hilman <khilman@baylibre.com> Signed-off-by: NMichael Turquette <mturquette@baylibre.com>
-
由 Michael Turquette 提交于
Break the AmLogic clock code up so that only the necessary parts are compiled and linked. The core code is selected by both arm and arm64 builds with COMMON_CLK_AMLOGIC. The individual drivers have their own config options as well. Tested-by: NKevin Hilman <khilman@baylibre.com> Signed-off-by: NMichael Turquette <mturquette@baylibre.com>
-
由 Michael Turquette 提交于
This patch creates a proper platform_driver for the meson8b clock controller. Use of CLK_OF_DECLARE is removed, and can be added back in later if very early registration of some clocks is required. Tested-by: NKevin Hilman <khilman@baylibre.com> Signed-off-by: NMichael Turquette <mturquette@baylibre.com>
-
由 Michael Turquette 提交于
Remove the composite clock registration function and helpers. Replace unnecessary configuration struct with static initialization of the desired clock type. To preserve git bisect this patch also flips the switch and starts using of_clk_add_hw_provider instead of the deprecated meson_clk_register_clks method. As a byproduct clk.c can be deleted. Tested-by: NKevin Hilman <khilman@baylibre.com> Signed-off-by: NMichael Turquette <mturquette@baylibre.com>
-
由 Michael Turquette 提交于
This clock is undocumented and always orphaned. Get rid of it until we have more complete clock tree documentation. Tested-by: NKevin Hilman <khilman@baylibre.com> Signed-off-by: NMichael Turquette <mturquette@baylibre.com>
-
由 Michael Turquette 提交于
Remove the cpu clock registration function and helpers. Replace unnecessary configuration struct with static initialization of the desired clock type. Ninja rename a5_clk to cpu_clk to better align with cpufreq convention. Tested-by: NKevin Hilman <khilman@baylibre.com> Signed-off-by: NMichael Turquette <mturquette@baylibre.com>
-
由 Michael Turquette 提交于
Remove the fixed factor registration function and helpers. Replace unnecessary configuration struct with static initialization of the desired clock type. Tested-by: NKevin Hilman <khilman@baylibre.com> Signed-off-by: NMichael Turquette <mturquette@baylibre.com>
-
由 Michael Turquette 提交于
Remove the pll registration function and helpers. Replace unnecessary configuration struct with static initialization of the desired clock type. Tested-by: NKevin Hilman <khilman@baylibre.com> Signed-off-by: NMichael Turquette <mturquette@baylibre.com>
-
由 Michael Turquette 提交于
Remove the fixed_rate registration function and helpers from clkc.[ch]. Replace unnecessary configuration struct with static initialization of the desired clock type. While we're here, begin the transition to a proper platform_driver and call of_clk_add_hw_provider with a shiny new struct clk_hw_onecell_data. Tested-by: NKevin Hilman <khilman@baylibre.com> Signed-off-by: NMichael Turquette <mturquette@baylibre.com>
-
由 Michael Turquette 提交于
The register offsets in the data sheet are confusing. Document them more thoroughly. Tested-by: NKevin Hilman <khilman@baylibre.com> Signed-off-by: NMichael Turquette <mturquette@baylibre.com>
-
- 16 4月, 2016 1 次提交
-
-
由 Stephen Boyd 提交于
This flag is a no-op now. Remove usage of the flag. Cc: Carlo Caione <carlo@caione.org> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
-
- 09 2月, 2016 1 次提交
-
-
由 Andreas Färber 提交于
As preparation for arm64 based mesongxbb, which pulls in this code once enabling ARCH_MESON, fix a size_t vs. unsigned int type mismatch. The loop uses a local unsigned int variable, so adopt that type, matching the header. Fixes: 7a29a869 ("clk: meson: Add support for Meson clock controller") Signed-off-by: NAndreas Färber <afaerber@suse.de> Acked-by: NCarlo Caione <carlo@endlessm.com> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
-
- 21 7月, 2015 1 次提交
-
-
由 Stephen Boyd 提交于
Clock provider drivers generally shouldn't include clk.h because it's the consumer API. Only include clk.h if it's actually used. Cc: Carlo Caione <carlo@endlessm.com> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
-
- 13 6月, 2015 1 次提交
-
-
由 Dan Carpenter 提交于
This error handling hopefully isn't needed but it make the static checkers happy. Signed-off-by: NDan Carpenter <dan.carpenter@oracle.com> Acked-by: NCarlo Caione <carlo@endlessm.com> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
-
- 06 6月, 2015 2 次提交
-
-
由 Carlo Caione 提交于
This patch adds support for the basic clocks found on the Amlogic Meson8b SoCs. Signed-off-by: NCarlo Caione <carlo@endlessm.com> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
-
由 Carlo Caione 提交于
This patchset adds the infrastructure for registering and managing the core clocks found on Amlogic MesonX SoCs. In particular: - PLLs - CPU clock - Fixed rate clocks, fixed factor clocks, ... Signed-off-by: NCarlo Caione <carlo@endlessm.com> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
-