1. 01 6月, 2017 2 次提交
  2. 15 5月, 2017 3 次提交
  3. 23 3月, 2017 11 次提交
  4. 30 1月, 2017 1 次提交
  5. 07 11月, 2016 1 次提交
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  8. 19 12月, 2015 3 次提交
  9. 09 12月, 2015 1 次提交
  10. 12 11月, 2015 2 次提交
  11. 27 10月, 2015 1 次提交
    • S
      mtd: fsmc_nand: Add BCH4 SW ECC support for SPEAr600 · e278fc71
      Stefan Roese 提交于
      This patch adds support for 4-bit ECC BCH4 for the SPEAr600 SoC. This can
      be used by boards equipped with a NAND chip that requires 4-bit ECC
      strength. The SPEAr600 HW ECC only supports 1-bit ECC strength.
      
      To enable SW BCH4, you need to specify this in your nand controller
      DT node:
      
      	nand-ecc-mode = "soft_bch";
      	nand-ecc-strength = <4>;
      	nand-ecc-step-size = <512>;
      
      Tested on a custom SPEAr600 board.
      Signed-off-by: NStefan Roese <sr@denx.de>
      Cc: Linus Walleij <linus.walleij@linaro.org>
      Cc: Viresh Kumar <viresh.kumar@linaro.org>
      [Brian: tweaked the comments a bit]
      Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
      e278fc71
  12. 14 10月, 2015 1 次提交
  13. 03 10月, 2015 2 次提交
  14. 07 5月, 2015 2 次提交
  15. 31 3月, 2015 1 次提交
  16. 20 10月, 2014 1 次提交
  17. 16 10月, 2014 1 次提交
  18. 08 1月, 2014 2 次提交