1. 28 10月, 2015 1 次提交
  2. 16 9月, 2015 1 次提交
    • T
      genirq: Remove irq argument from irq flow handlers · bd0b9ac4
      Thomas Gleixner 提交于
      Most interrupt flow handlers do not use the irq argument. Those few
      which use it can retrieve the irq number from the irq descriptor.
      
      Remove the argument.
      
      Search and replace was done with coccinelle and some extra helper
      scripts around it. Thanks to Julia for her help!
      Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
      Cc: Julia Lawall <Julia.Lawall@lip6.fr>
      Cc: Jiang Liu <jiang.liu@linux.intel.com>
      bd0b9ac4
  3. 12 9月, 2015 1 次提交
  4. 27 8月, 2015 7 次提交
  5. 21 8月, 2015 1 次提交
  6. 20 8月, 2015 10 次提交
    • V
      09074950
    • Y
      ARC: change some branchs to jumps to resolve linkage errors · 6de6066c
      Yuriy Kolerov 提交于
      When kernel's binary becomes large enough (32M and more) errors
      may occur during the final linkage stage. It happens because
      the build system uses short relocations for ARC  by default.
      This problem may be easily resolved by passing -mlong-calls
      option to GCC to use long absolute jumps (j) instead of short
      relative branchs (b).
      
      But there are fragments of pure assembler code exist which use
      branchs in inappropriate places and cause a linkage error because
      of relocations overflow.
      
      First of these fragments is .fixup insertion in futex.h and
      unaligned.c. It inserts a code in the separate section (.fixup)
      with branch instruction. It leads to the linkage error when
      kernel becomes large.
      
      Second of these fragments is calling scheduler's functions
      (common kernel code) from entry.S of ARC's code. When kernel's
      binary becomes large it may lead to the linkage error because
      scheduler may occur far enough from ARC's code in the final
      binary.
      Signed-off-by: NYuriy Kolerov <yuriy.kolerov@synopsys.com>
      Signed-off-by: NVineet Gupta <vgupta@synopsys.com>
      6de6066c
    • V
      ARC: ensure futex ops are atomic in !LLSC config · eb2cd8b7
      Vineet Gupta 提交于
      W/o hardware assisted atomic r-m-w the best we can do is to disable
      preemption.
      
      Cc: David Hildenbrand <dahi@linux.vnet.ibm.com>
      Cc: Peter Zijlstra (Intel) <peterz@infradead.org>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: Michel Lespinasse <walken@google.com>
      Signed-off-by: NVineet Gupta <vgupta@synopsys.com>
      eb2cd8b7
    • V
      ARC: Enable HAVE_FUTEX_CMPXCHG · 5e057429
      Vineet Gupta 提交于
      ARC doesn't need the runtime detection of futex cmpxchg op
      
      Cc: Peter Zijlstra (Intel) <peterz@infradead.org>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Signed-off-by: NVineet Gupta <vgupta@synopsys.com>
      5e057429
    • V
      ARC: make futex_atomic_cmpxchg_inatomic() return bimodal · 882a95ae
      Vineet Gupta 提交于
      Callers of cmpxchg_futex_value_locked() in futex code expect bimodal
      return value:
        !0 (essentially -EFAULT as failure)
         0 (success)
      
      Before this patch, the success return value was old value of futex,
      which could very well be non zero, causing caller to possibly take the
      failure path erroneously.
      
      Fix that by returning 0 for success
      
      (This fix was done back in 2011 for all upstream arches, which ARC
      obviously missed)
      
      Cc: Peter Zijlstra (Intel) <peterz@infradead.org>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: Michel Lespinasse <walken@google.com>
      Signed-off-by: NVineet Gupta <vgupta@synopsys.com>
      882a95ae
    • V
      ARC: futex cosmetics · ed574e2b
      Vineet Gupta 提交于
      Cc: Peter Zijlstra (Intel) <peterz@infradead.org>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: Michel Lespinasse <walken@google.com>
      Signed-off-by: NVineet Gupta <vgupta@synopsys.com>
      ed574e2b
    • V
      ARC: add barriers to futex code · 31d30c82
      Vineet Gupta 提交于
      The atomic ops on futex need to provide the full barrier just like
      regular atomics in kernel.
      
      Also remove pagefault_enable/disable in futex_atomic_cmpxchg_inatomic()
      as core code already does that
      
      Cc: David Hildenbrand <dahi@linux.vnet.ibm.com>
      Cc: Peter Zijlstra (Intel) <peterz@infradead.org>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: Michel Lespinasse <walken@google.com>
      Signed-off-by: NVineet Gupta <vgupta@synopsys.com>
      31d30c82
    • A
      ARCv2: IOC: Allow boot time disable · 1648c70d
      Alexey Brodkin 提交于
      Signed-off-by: NAlexey Brodkin <abrodkin@synopsys.com>
      Signed-off-by: NVineet Gupta <vgupta@synopsys.com>
      1648c70d
    • V
      ARCv2: SLC: Allow boot time disable · 79335a2c
      Vineet Gupta 提交于
      Signed-off-by: NVineet Gupta <vgupta@synopsys.com>
      79335a2c
    • A
      ARCv2: Support IO Coherency and permutations involving L1 and L2 caches · f2b0b25a
      Alexey Brodkin 提交于
      In case of ARCv2 CPU there're could be following configurations
      that affect cache handling for data exchanged with peripherals
      via DMA:
       [1] Only L1 cache exists
       [2] Both L1 and L2 exist, but no IO coherency unit
       [3] L1, L2 caches and IO coherency unit exist
      
      Current implementation takes care of [1] and [2].
      Moreover support of [2] is implemented with run-time check
      for SLC existence which is not super optimal.
      
      This patch introduces support of [3] and rework of DMA ops
      usage. Instead of doing run-time check every time a particular
      DMA op is executed we'll have 3 different implementations of
      DMA ops and select appropriate one during init.
      
      As for IOC support for it we need:
       [a] Implement empty DMA ops because IOC takes care of cache
           coherency with DMAed data
       [b] Route dma_alloc_coherent() via dma_alloc_noncoherent()
           This is required to make IOC work in first place and also
           serves as optimization as LD/ST to coherent buffers can be
           srviced from caches w/o going all the way to memory
      Signed-off-by: NAlexey Brodkin <abrodkin@synopsys.com>
      [vgupta:
        -Added some comments about IOC gains
        -Marked dma ops as static,
        -Massaged changelog a bit]
      Signed-off-by: NVineet Gupta <vgupta@synopsys.com>
      f2b0b25a
  7. 11 8月, 2015 1 次提交
  8. 07 8月, 2015 1 次提交
  9. 05 8月, 2015 1 次提交
    • V
      ARC: Make pt_regs regs unsigned · 87ce6280
      Vineet Gupta 提交于
      KGDB fails to build after f51e2f19 ("ARC: make sure instruction_pointer()
      returns unsigned value")
      
      The hack to force one specific reg to unsigned backfired. There's no
      reason to keep the regs signed after all.
      
      |  CC      arch/arc/kernel/kgdb.o
      |../arch/arc/kernel/kgdb.c: In function 'kgdb_trap':
      | ../arch/arc/kernel/kgdb.c:180:29: error: lvalue required as left operand of assignment
      |   instruction_pointer(regs) -= BREAK_INSTR_SIZE;
      Reported-by: NYuriy Kolerov <yuriy.kolerov@synopsys.com>
      Fixes: f51e2f19 ("ARC: make sure instruction_pointer() returns unsigned value")
      Cc: Alexey Brodkin <abrodkin@synopsys.com>
      Signed-off-by: NVineet Gupta <vgupta@synopsys.com>
      87ce6280
  10. 04 8月, 2015 7 次提交
  11. 03 8月, 2015 1 次提交
  12. 01 8月, 2015 1 次提交
    • T
      arc/irq: Prepare idu_cascade_isr for irq argument removal · badae6bc
      Thomas Gleixner 提交于
      The irq argument of most interrupt flow handlers is unused or merily
      used instead of a local variable. The handlers which need the irq
      argument can retrieve the irq number from the irq descriptor.
      
      Search and update was done with coccinelle and the invaluable help of
      Julia Lawall.
      Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
      Cc: Julia Lawall <Julia.Lawall@lip6.fr>
      Cc: Vineet Gupta <vgupta@synopsys.com>
      badae6bc
  13. 27 7月, 2015 3 次提交
  14. 23 7月, 2015 1 次提交
  15. 20 7月, 2015 3 次提交