1. 30 10月, 2013 1 次提交
    • M
      MIPS: DECstation I/O ASIC DMA interrupt classes · 0fabe102
      Maciej W. Rozycki 提交于
      This change complements commits d0da7c002f7b2a93582187a9e3f73891a01d8ee4
      [MIPS: DEC: Convert to new irq_chip functions] and
      5359b938 [MIPS: DECstation I/O ASIC DMA
      interrupt handling fix] and implements automatic handling of the two
      classes of DMA interrupts the I/O ASIC implements, informational and
      errors.
      
      Informational DMA interrupts do not stop the transfer and use the
      `handle_edge_irq' handler that clears the request right away so that
      another request may be recorded while the previous is being handled.
      
      DMA error interrupts stop the transfer and require a corrective action
      before DMA can be reenabled.  Therefore they use the `handle_fasteoi_irq'
      handler that only clears the request on the way out.  Because MIPS
      processor interrupt inputs, one of which the I/O ASIC's interrupt
      controller is cascaded to, are level-triggered it is recommended that
      error DMA interrupt action handlers are registered with the IRQF_ONESHOT
      flag set so that they are run with the interrupt line masked.
      
      This change removes the export of clear_ioasic_dma_irq that now does not
      have to be called by device drivers to clear interrupts explicitly
      anymore.  Originally these interrupts were cleared in the .end handler of
      the `irq_chip' structure, before it was removed.
      Signed-off-by: NMaciej W. Rozycki <macro@linux-mips.org>
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/5874/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      0fabe102
  2. 13 9月, 2013 1 次提交
    • M
      MIPS: DECstation I/O ASIC DMA interrupt handling fix · 5359b938
      Maciej W. Rozycki 提交于
      This change complements commit d0da7c002f7b2a93582187a9e3f73891a01d8ee4
      and brings clear_ioasic_irq back, renaming it to clear_ioasic_dma_irq at
      the same time, to make I/O ASIC DMA interrupts functional.
      
      Unlike ordinary I/O ASIC interrupts DMA interrupts need to be deasserted
      by software by writing 0 to the respective bit in I/O ASIC's System
      Interrupt Register (SIR), similarly to how CP0.Cause.IP0 and CP0.Cause.IP1
      bits are handled in the CPU (the difference is SIR DMA interrupt bits are
      R/W0C so there's no need for an RMW cycle).  Otherwise the handler is
      reentered over and over again.
      
      The only current user is the DEC LANCE Ethernet driver and its extremely
      uncommon DMA memory error handler that does not care when exactly the
      interrupt is cleared.  Anticipating the use of DMA interrupts by the Zilog
      SCC driver this change however exports clear_ioasic_dma_irq for device
      drivers to choose the right application-specific sequence to clear the
      request explicitly rather than calling it implicitly in the .irq_eoi
      handler of `struct irq_chip'.  Previously these interrupts were cleared in
      the .end handler of the said structure, before it was removed.
      Signed-off-by: NMaciej W. Rozycki <macro@linux-mips.org>
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/5826/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      5359b938
  3. 29 3月, 2011 1 次提交
  4. 26 3月, 2011 1 次提交
  5. 04 8月, 2009 1 次提交
  6. 07 2月, 2007 1 次提交
  7. 07 12月, 2006 2 次提交
  8. 30 11月, 2006 2 次提交
    • A
      [MIPS] use generic_handle_irq, handle_level_irq, handle_percpu_irq · 1417836e
      Atsushi Nemoto 提交于
      Further incorporation of generic irq framework.  Replacing __do_IRQ()
      by proper flow handler would make the irq handling path a bit simpler
      and faster.
      
      * use generic_handle_irq() instead of __do_IRQ().
      * use handle_level_irq for obvious level-type irq chips.
      * use handle_percpu_irq for irqs marked as IRQ_PER_CPU.
      * setup .eoi routine for irq chips possibly used with handle_percpu_irq.
      Signed-off-by: NAtsushi Nemoto <anemo@mba.ocn.ne.jp>
      Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      1417836e
    • A
      [MIPS] IRQ cleanups · 1603b5ac
      Atsushi Nemoto 提交于
      This is a big irq cleanup patch.
      
      * Use set_irq_chip() to register irq_chip.
      * Initialize .mask, .unmask, .mask_ack field.  Functions for these
        method are already exist in most case.
      * Do not initialize .startup, .shutdown, .enable, .disable fields if
        default routines provided by irq_chip_set_defaults() were suitable.
      * Remove redundant irq_desc initializations.
      * Remove unnecessary local_irq_save/local_irq_restore, spin_lock.
      
      With this cleanup, it would be easy to switch to slightly lightwait
      irq flow handlers (handle_level_irq(), etc.) instead of __do_IRQ().
      
      Though whole this patch is quite large, changes in each irq_chip are
      not quite simple.  Please review and test on your platform.  Thanks.
      Signed-off-by: NAtsushi Nemoto <anemo@mba.ocn.ne.jp>
      Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      1603b5ac
  9. 14 7月, 2006 1 次提交
  10. 30 6月, 2006 1 次提交
    • I
      [PATCH] genirq: rename desc->handler to desc->chip · d1bef4ed
      Ingo Molnar 提交于
      This patch-queue improves the generic IRQ layer to be truly generic, by adding
      various abstractions and features to it, without impacting existing
      functionality.
      
      While the queue can be best described as "fix and improve everything in the
      generic IRQ layer that we could think of", and thus it consists of many
      smaller features and lots of cleanups, the one feature that stands out most is
      the new 'irq chip' abstraction.
      
      The irq-chip abstraction is about describing and coding and IRQ controller
      driver by mapping its raw hardware capabilities [and quirks, if needed] in a
      straightforward way, without having to think about "IRQ flow"
      (level/edge/etc.) type of details.
      
      This stands in contrast with the current 'irq-type' model of genirq
      architectures, which 'mixes' raw hardware capabilities with 'flow' details.
      The patchset supports both types of irq controller designs at once, and
      converts i386 and x86_64 to the new irq-chip design.
      
      As a bonus side-effect of the irq-chip approach, chained interrupt controllers
      (master/slave PIC constructs, etc.) are now supported by design as well.
      
      The end result of this patchset intends to be simpler architecture-level code
      and more consolidation between architectures.
      
      We reused many bits of code and many concepts from Russell King's ARM IRQ
      layer, the merging of which was one of the motivations for this patchset.
      
      This patch:
      
      rename desc->handler to desc->chip.
      
      Originally i did not want to do this, because it's a big patch.  But having
      both "desc->handler", "desc->handle_irq" and "action->handler" caused a
      large degree of confusion and made the code appear alot less clean than it
      truly is.
      
      I have also attempted a dual approach as well by introducing a
      desc->chip alias - but that just wasnt robust enough and broke
      frequently.
      
      So lets get over with this quickly.  The conversion was done automatically
      via scripts and converts all the code in the kernel.
      
      This renaming patch is the first one amongst the patches, so that the
      remaining patches can stay flexible and can be merged and split up
      without having some big monolithic patch act as a merge barrier.
      
      [akpm@osdl.org: build fix]
      [akpm@osdl.org: another build fix]
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
      Signed-off-by: NAndrew Morton <akpm@osdl.org>
      Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      d1bef4ed
  11. 17 4月, 2005 1 次提交
    • L
      Linux-2.6.12-rc2 · 1da177e4
      Linus Torvalds 提交于
      Initial git repository build. I'm not bothering with the full history,
      even though we have it. We can create a separate "historical" git
      archive of that later if we want to, and in the meantime it's about
      3.2GB when imported into git - space that would just make the early
      git days unnecessarily complicated, when we don't have a lot of good
      infrastructure for it.
      
      Let it rip!
      1da177e4