The offset seems to have been copied from the sata clk. Fix it so
that enabling the crypto engine source clk works.
Tested-by: NSrinivas Kandagatla <srinivas.kandagatla@linaro.org>
Tested-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Fixes: 5f775498 ("clk: qcom: Fully support apq8064 global clock control")
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Conflicts:
	drivers/clk/Kconfig

drivers/clk/ti/clk-814x.c:34:12: warning: symbol 'dm814x_adpll_early_init' was not declared. Should it be static?
drivers/clk/ti/clk-814x.c:58:12: warning: symbol 'dm814x_adpll_enable_init_clocks' was not declared. Should it be static?
drivers/clk/ti/adpll.c:465 ti_adpll_recalc_rate() warn: should '__readw(d->regs + 20) << 18' be a 64 bit type?
drivers/clk/ti/adpll.c:945 ti_adpll_probe() error: we previously assumed 'd->clocks' could be null (see line 921)

The last one looks like a real bug because we don't return an
error on allocation failure.

Cc: Tero Kristo <t-kristo@ti.com>
Tested-by: NTony Lindgren <tony@atomide.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

The arch independent drivers can be build testeed with
COMPILE_TEST. Let's allow that for drivers/clk/ti.
Signed-off-by: NTony Lindgren <tony@atomide.com>
Signed-off-by: NMichael Turquette <mturquette@baylibre.com>

On dm814x we have 13 ADPLLs with 3 to 4 outputs on each. The
ADPLLs have several dividers and muxes controlled by a shared
control register for each PLL.

Note that for the clocks to work as device drivers for booting on
dm814x, this patch depends on "ARM: OMAP2+: Change core_initcall
levels to postcore_initcall" that has already been merged.

Also note that this patch does not implement clk_set_rate for the
PLL, that will be posted later on when available.

Cc: Stephen Boyd <sboyd@codeaurora.org>
Acked-by: NTero Kristo <t-kristo@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>
Signed-off-by: NMichael Turquette <mturquette@baylibre.com>

The clk_rcg_pixel_set_rate clk_op sets up the pre-divider by reading
its current value from the NS register.

Using the pre-divider wasn't really intended when creating these ops.
The pixel RCG was only intended to achieve fractional multiplication
provided in the pixel_table array. Leaving the pre-divider to the
existing register value results in a wrong pixel clock when the
bootloader sets up the display. This was left unidentified because
the IFC6410 Plus board on which this was verified didn't have a
bootloader that configured the display.

Don't set the RCG pre-divider in freq_tbl to the existing NS register
value. Force it to 1 and only use the M/N counter to achieve the desired
fractional multiplication.

Cc: Vinay Simha <vinaysimha@inforcecomputing.com>
Signed-off-by: NArchit Taneja <architt@codeaurora.org>
Tested-by: NJohn Stultz <john.stultz@linaro.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Sparse complains here because we dropped the __iomem annotation
when casting the aligned address. Add __iomem back so that sparse
stops complaining.

Cc: Yoshinori Sato <ysato@users.sourceforge.jp>
Cc: <uclinux-h8-devel@lists.sourceforge.jp>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

The check for < 0 is impossible now that
of_clk_get_parent_count() returns an unsigned int. Simplify the
code and update the types.

Cc: Hans de Goede <hdegoede@redhat.com>
Cc: Jean-Christophe Plagniol-Villard <plagnioj@jcrosoft.com>
Acked-by: NTomi Valkeinen <tomi.valkeinen@ti.com>
Cc: <linux-fbdev@vger.kernel.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

The check for < 0 is impossible now that
of_clk_get_parent_count() returns an unsigned int. Simplify the
code and update the types.
Acked-by: NFelipe Balbi <balbi@kernel.org>
Cc: <linux-usb@vger.kernel.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Change the types here to unsigned int instead of int and update
the checks for == 0 instead < 1 to be more explicit about what's
going on now that of_clk_get_parent_count() has changed return
types.

Cc: Tero Kristo <t-kristo@ti.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

The return type of of_clk_get_parent_count() is an unsigned int
now, so let's update the code here to be more explicit about the
range of values we can test for.

Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

The checks for < 0 are impossible now that
of_clk_get_parent_count() returns an unsigned int. Simplify the
code and update the types.

Cc: Gabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

The checks for < 1 can be simplified now that
of_clk_get_parent_count() returns an unsigned int. Update the
code to reflect the int to unsigned int change.

Cc: Yoshinori Sato <ysato@users.sourceforge.jp>
Cc: <uclinux-h8-devel@lists.sourceforge.jp>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

The check for < 0 is impossible now that
of_clk_get_parent_count() returns an unsigned int. Simplify the
code and update the type here.
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

These checks for < 0 are impossible now that
of_clk_get_parent_count() returns an unsigned int. Change the
checks for == 0 and update the type.

Cc: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Russell King recently pointed out a bug in the clk-gpio code
where it fails to register the clk if of_clk_get_parent_count()
returns an error because the "clocks" property isn't present in
the DT node. If we're trying to count parents from DT we'd like
to know the count, not if there is a "clocks" property or not.
Furthermore, some drivers are assigning the return value to their
clk_init_data::num_parents member which is unsigned, leading to
potentially large numbers of parents when the property isn't
present.

Let's change the API to return an unsigned int instead of an int.
All the callers just want to know the count anyway, and this
avoids the bug that was in the clk-gpio driver.
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

of_clk_init() uses for_each_matching_node_and_match() to find clock
providers, which returns all matching device nodes, whether they are
enabled or not. Hence clock providers that are disabled explicitly in DT
using e.g.

	"status = "disabled";

are still activated.

Add a check to ignore device nodes that are not enabled, like
of_irq_init() does.
Reported-by: NRamesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Let's compare the degrees from clk_set_rate with
clk->core->phase. If the requested degrees is already
there, skip the following steps.
Signed-off-by: NShawn Lin <shawn.lin@rock-chips.com>
[sboyd@codeaurora.org: s/drgrees/degrees/ in commit text]
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Added missing CTRL and DIV clock register definitions for:
PCM, SLIM, TCNT, TEC, TD0, TD1

Register information taken from:
https://rawgit.com/msperl/rpi-registers/master/rpi-registers.html#CM
which extracted the information from the header files shared by
Broadcom/rpi foundation in this file:
http://www.broadcom.com/docs/support/videocore/Brcm_Android_ICS_Graphics_Stack.tar.gzSigned-off-by: NMartin Sperl <kernel@martin.sperl.org>
Reviewed-by: NEric Anholt <eric@anholt.net>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

As of 9b5ba0df ("ARM: shmobile: Introduce ARCH_RENESAS") all platforms
that use Renesas clock drivers now select ARCH_RENESAS. As it is present in
drivers/clk/Makefile ARCH_SHMOBILE_MULTI may now be removed.

This is part of an ongoing process to migrate from ARCH_SHMOBILE to
ARCH_RENESAS the motivation for which being that RENESAS seems to be a more
appropriate name than SHMOBILE for the majority of Renesas ARM based SoCs.
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
Acked-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Pull Samsung clk driver changes from Sylwester Nawrocki:

Mostly correction of errors in the exynos5433 SoC
clocks definition, dropping read-only registers
from the suspend/resume register save/restore list
and exposition of two clocks required for the
exynos5433 HDMI subsystem operation.

* tag 'clk-samsung-4.6' of git://linuxtv.org/snawrocki/samsung:
  clk: samsung: exynos5433: Fix wrong registers of PCLK_GSCL_SMMU clocks
  clk: samsung: exynos5433: Fix mout_aclk_cam1*_user clocks definition
  clk: samsung: exynos5433: Drop RO registers from the save/restore lists
  clk: samsung: exynos5433: Fix definitions of SCLK ISP SENSOR0 clocks
  clk: samsung: exynos5433: Fix definitions of MUX_SEL_CAM04 clocks
  clk: samsung: exynos5433: Fix typos in *_ISP_MPWM clock names
  clk/samsung: exynos5433: add pclk_decon clock
  clk/samsung: exynos5433: add definitions of HDMI-PHY output clocks

The core clock does not depend on corediv, so enabling corediv
based on the clock is not really correct.  Move the corediv
config option from the clock driver Kconfig to the mvebu Kconfig
so that it can be enabled by the MACH option instead.

This also enables corediv on Armada 375 and 38X, which was
previously missing.
Signed-off-by: NKevin Smith <kevin.smith@elecsyscorp.com>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Gregory CLEMENT <gregory.clement@free-electrons.com>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

There is no corediv clock on Armada XP, so this is unnecessary.
Signed-off-by: NKevin Smith <kevin.smith@elecsyscorp.com>
Acked-by: NMichael Turquette <mturquette@baylibre.com>
Acked-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Despite care take to allocate clocks state containers the
SP810 driver actually just supports creating one instance:
all clocks registered for every instance will end up with the
exact same name and __clk_init() will fail.

Rename the timclken<0> .. timclken<n> to sp810_<instance>_<n>
so every clock on every instance gets a unique name.

This is necessary for the RealView PBA8 which has two SP810
blocks: the second block will not register its clocks unless
every clock on every instance is unique and results in boot
logs like this:

------------[ cut here ]------------
WARNING: CPU: 0 PID: 0 at ../drivers/clk/versatile/clk-sp810.c:137
  clk_sp810_of_setup+0x110/0x154()
Modules linked in:
CPU: 0 PID: 0 Comm: swapper/0 Not tainted
4.5.0-rc2-00030-g352718fc39f6-dirty #225
Hardware name: ARM RealView Machine (Device Tree Support)
[<c00167f8>] (unwind_backtrace) from [<c0013204>]
             (show_stack+0x10/0x14)
[<c0013204>] (show_stack) from [<c01a049c>]
             (dump_stack+0x84/0x9c)
[<c01a049c>] (dump_stack) from [<c0024990>]
             (warn_slowpath_common+0x74/0xb0)
[<c0024990>] (warn_slowpath_common) from [<c0024a68>]
             (warn_slowpath_null+0x1c/0x24)
[<c0024a68>] (warn_slowpath_null) from [<c051eb44>]
             (clk_sp810_of_setup+0x110/0x154)
[<c051eb44>] (clk_sp810_of_setup) from [<c051e3a4>]
             (of_clk_init+0x12c/0x1c8)
[<c051e3a4>] (of_clk_init) from [<c0504714>]
             (time_init+0x20/0x2c)
[<c0504714>] (time_init) from [<c0501b18>]
             (start_kernel+0x244/0x3c4)
[<c0501b18>] (start_kernel) from [<7000807c>] (0x7000807c)
---[ end trace cb88537fdc8fa200 ]---

Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Pawel Moll <pawel.moll@arm.com>
Fixes: 6e973d2c "clk: vexpress: Add separate SP810 driver"
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

This config was used for the ARM port so that it could use a
machine specific clkdev.h include, but those are all gone now.
The MIPS architecture is the last user, and from what I can tell
it doesn't actually use it anyway, so let's remove the config all
together.

Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: <linux-mips@linux-mips.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Reviewed-by: NJoshua Henderson <joshua.henderson@microchip.com>

* clk-ipq4019:
  clk: qcom: Add IPQ4019 Global Clock Controller support

This patch adds support for the global clock controller found on
the IPQ4019 based devices. This includes UART, I2C, SPI etc.
Signed-off-by: NPradeep Banavathi <pradeepb@codeaurora.org>
Signed-off-by: NSenthilkumar N L <snlakshm@codeaurora.org>
Signed-off-by: NVaradarajan Narayanan <varada@codeaurora.org>
Signed-off-by: NMatthew McClintock <mmcclint@codeaurora.org>
Acked-by: NAndy Gross <andy.gross@linaro.org>
[sboyd@codeaurora.org: Drop 0x16024 enable_reg in crypto_ahb]
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

We forgot to free this clock when we return early in this code.

Cc: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

This fixes register assignment in the CLK_PCLK_SMMU_GSCL{1,2}
clocks definition.
Signed-off-by: NJonghwa Lee <jonghwa3.lee@samsung.com>
Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>

Control bits for the ACLK_CAM1_552_USER and ACLK_CAM1_400_USER
mux clocks are in MUX_SEL_CAM10, not MUX_SEL_CAM01 register.
Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>

Restoring read-only registers is of not much effect, drop them
from the respective lists.
Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>

This fixes bit field offsets in the CMU_TOP CLK_DIV_SCLK_ISP_SENSOR_{A,B}
clock definitions.
Signed-off-by: NMarek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>

This corrects assignment of bit offsets of the MUX_SEL_CAM04 register
to the respective mux clocks.
Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>

We were not checking the return from devm_add_action() which can fail.
Start using the helper devm_add_action_or_reset() and return directly
as we know that the cleanup has been done by this helper.
Signed-off-by: NSudip Mukherjee <sudip.mukherjee@codethink.co.uk>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

This fixes "MPWM" -> "WPWM" typo in 3 *ISP_MWPM clock definitions.
Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>

__clk_init() was renamed to __clk_core_init() but these comments
weren't updated.

Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

This reverts commit 858d5881.

Joachim reports that this commit breaks lpc18xx boot. This is
because the hardware has circular clk topology where PLLs can
feed into dividers and the same dividers can feed into the PLLs.
The hardware is designed this way so that you can choose to put
the divider before the PLL or after the PLL depending on what you
configure to be the parent of the divider and what you configure
to be the parent of the PLL.

So let's drop this patch for now because we have hardware that
actually has loops. A future patch could check for circular
parents when we change parents and fail the switch, but that's
probably best left to some debugging Kconfig option so that we
don't suffer the sanity checking cost all the time.
Reported-by: NJoachim Eastwood <manabian@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

There are some Arria10 clocks of type "altr,socfpga-a10-perip-clk" that can
have multiple parents. Fix up the __socfpga_periph_init() to call
of_clk_parent_fill() that will return the appropriate number of parents.

Also, update __socfpga_gate_init() to call of_clk_parent_fill() helper
function.
Signed-off-by: NDinh Nguyen <dinguyen@opensource.altera.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Convert DPLL support code to use clk_hw pointers for reference and bypass
clocks. This allows us to use clk_hw_* APIs for accessing any required
parameters for these clocks, avoiding some locking problems at least with
DPLL enable code; this used clk_get_rate which uses mutex but isn't
good under clk_enable / clk_disable.
Signed-off-by: NTero Kristo <t-kristo@ti.com>
Acked-by: NTony Lindgren <tony@atomide.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

* clk-fixes:
  clk: ti: omap3+: dpll: use non-locking version of clk_get_rate