- 11 7月, 2007 36 次提交
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由 Ralf Baechle 提交于
Using another systems defines is a safe way to get your code broken by accident when that system is removed. Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Atsushi Nemoto 提交于
This patch is an workaround for these sparse warnings: linux/include/linux/calc64.h:25:17: warning: symbol '__quot' shadows an earlier one linux/include/linux/calc64.h:25:17: originally declared here linux/include/linux/calc64.h:25:17: warning: symbol '__mod' shadows an earlier one linux/include/linux/calc64.h:25:17: originally declared here Signed-off-by: NAtsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Ralf Baechle 提交于
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Ralf Baechle 提交于
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Yoichi Yuasa 提交于
Signed-off-by: NYoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Chris Dearman 提交于
Signed-off-by: NChris Dearman <chris@mips.com> Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Atsushi Nemoto 提交于
TX39XX and TX49XX have "reserved" segment in CKSEG3 area. 0xff000000-0xff3fffff on TX49XX and 0xff000000-0xfffeffff on TX39XX are reserved (unmapped, uncached). Controllers on these SoCs are placed in this segment. This patch add plat_ioremap() and plat_iounmap() to override default behavior and implement these hooks for TX39/TX49. Signed-off-by: NAtsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Atsushi Nemoto 提交于
Use rtc-rs5c348 and at25 spi protocol driver and spi_txx9 spi controller driver instead of platform dependent codes. This patch also removes dependencies to old RTC interfaces such as rtc_mips_get_time, etc. Signed-off-by: NAtsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Thomas Bogendoerfer 提交于
- use RTC_CLASS instead of GEN_RTC - get rid of ds1216 in favour of a RTC_CLASS driver - use correct console device for older RM400 - use physical addresses for 82596 device - use 128 byte L1 cache line size (this is needed because most of the SNI caches are using 128 L2 cache lines) Signed-off-by: NThomas Bogendoerfer <tsbogend@alpha.franken.de> Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Marc St-Jean 提交于
Patch to add PCI support for the PMC-Sierra MSP71xx devices. Signed-off-by: NMarc St-Jean <Marc_St-Jean@pmc-sierra.com> Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Marc St-Jean 提交于
Patch to add mips common support for the PMC-Sierra MSP71xx devices. Signed-off-by: NMarc St-Jean <Marc_St-Jean@pmc-sierra.com> Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Marc St-Jean 提交于
Patch to add core platform support for the PMC-Sierra MSP71xx devices. Signed-off-by: NMarc St-Jean <Marc_St-Jean@pmc-sierra.com> Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Adrian Bunk 提交于
Signed-off-by: NAdrian Bunk <bunk@stusta.de> Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Songmao Tian 提交于
Signed-off-by: NFuxin Zhang <zhangfx@lemote.com> Signed-off-by: NSongmao Tian <tiansm@lemote.com> Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Fuxin Zhang 提交于
Signed-off-by: NFuxin Zhang <zhangfx@lemote.com> Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Ralf Baechle 提交于
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Ralf Baechle 提交于
Which will cut down the cost of RDHWR $29 which is used to obtain the TLS pointer and so far being emulated in software down to a single cycle operation. Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Ralf Baechle 提交于
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Ralf Baechle 提交于
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Franck Bui-Huu 提交于
Signed-off-by: NFranck Bui-Huu <fbuihuu@gmail.com> Signed-off-by: NRalf Baechle <ralf@linux-mips.org> delete mode 100644 arch/mips/configs/ocelot_c_defconfig delete mode 100644 arch/mips/momentum/ocelot_c/Makefile delete mode 100644 arch/mips/momentum/ocelot_c/cpci-irq.c delete mode 100644 arch/mips/momentum/ocelot_c/dbg_io.c delete mode 100644 arch/mips/momentum/ocelot_c/irq.c delete mode 100644 arch/mips/momentum/ocelot_c/ocelot_c_fpga.h delete mode 100644 arch/mips/momentum/ocelot_c/platform.c delete mode 100644 arch/mips/momentum/ocelot_c/prom.c delete mode 100644 arch/mips/momentum/ocelot_c/reset.c delete mode 100644 arch/mips/momentum/ocelot_c/setup.c delete mode 100644 arch/mips/momentum/ocelot_c/uart-irq.c delete mode 100644 arch/mips/pci/fixup-ocelot-c.c delete mode 100644 arch/mips/pci/pci-ocelot-c.c
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由 Ralf Baechle 提交于
This is to break the code of people who think they are supposed to scribble into the pci device structure - it's off limits. Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Yoichi Yuasa 提交于
Signed-off-by: NYoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Atsushi Nemoto 提交于
Signed-off-by: NAtsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Franck Bui-Huu 提交于
The current implementation of __pa() for 64-bits kernels with 32-bits symbols is broken. In this configuration, we need 2 values for PAGE_OFFSET, one in XKPHYS and the other in CKSEG0 space. When the value in CKSEG0 space is used, it doesn't take into account of PHYS_OFFSET. Even worse we can't redefine this value. The patch restores CPHYSADDR() but in __pa()'s implementation because it removes the need of 2 PAGE_OFFSET. OTOH, CPHYSADDR() is quite bad when dealing with mapped kernels. So this patch assumes there's no need to deal with such kernel in 64-bits world. Signed-off-by: NFranck Bui-Huu <fbuihuu@gmail.com> Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Franck Bui-Huu 提交于
Signed-off-by: NFranck Bui-Huu <fbuihuu@gmail.com> Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Franck Bui-Huu 提交于
For platforms that use PHYS_OFFSET and do not use a mapped kernel, this patch automatically adds PHYS_OFFSET into PAGE_OFFSET. Therefore there are no more needs for them to redefine PAGE_OFFSET. For mapped kernel, they need to redefine PAGE_OFFSET anyways. Signed-off-by: NFranck Bui-Huu <fbuihuu@gmail.com> Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Franck Bui-Huu 提交于
PAGE_OFFSET definition is now using CAC_BASE by default. This patch also reorder some macros to make them appear in the same order for both 32 and 64 bits configs. It also makes use of const.h generic header file to annotate constants. Signed-off-by: NFranck Bui-Huu <fbuihuu@gmail.com> Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Franck Bui-Huu 提交于
Before this patch, when a platform needed to customize one constant in spaces.h, they need to redefine all of them. Now they can just redefine one constant and include the generic file header at the end: #include <asm/mach-generic/spaces.h> This patch doesn't allow to redefine CAC_BASE, IO_BASE and UNCAC_BASE for 32 bits platforms because there's no need to do so. This will avoid some macro duplications. It's important specially if we'll add complex macros. Signed-off-by: NFranck Bui-Huu <fbuihuu@gmail.com> Signed-off-by: NRalf Baechle <ralf@linux-mips.org> delete mode 100644 include/asm-mips/mach-ip32/spaces.h
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由 Ralf Baechle 提交于
It shares no code at all. While at it also fix up the beginning bitrot. Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Ralf Baechle 提交于
No point in adding yet another #ifdef for Loongson since all this mask is being used for is converting an XKPHYS address into a physical address anyway. So replace all definitions by one with the highest architectural possible value. Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Florian Fainelli 提交于
This patch adds support for the generic GPIO API to Au1x00 boards. It requires the generic GPIO patch for MIPS boards by Yoichi Yuasa. Now there is a MIPS target using it, can you queue these patchset for 2.6.22 ? Thank you very much in advance. Signed-off-by: NFlorian Fainelli <florian.fainelli@telecomint.eu> Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Atsushi Nemoto 提交于
Create fallback gpio.h which only contains prototypes for gpio API. Signed-off-by: NAtsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Yoichi Yuasa 提交于
Signed-off-by: NYoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Adrian Bunk 提交于
Signed-off-by: NAdrian Bunk <bunk@stusta.de> Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Adrian Bunk 提交于
"extern inline" will have different semantics with gcc 4.3, and "static inline" is correct here. Signed-off-by: NAdrian Bunk <bunk@stusta.de> Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Yoichi Yuasa 提交于
Signed-off-by: NYoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 10 7月, 2007 1 次提交
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由 Junio C Hamano 提交于
This updates the DMA whitelist in MIPS specific au1xxx ide driver to use NULL instead of "ALL" as the wildcard. Signed-off-by: NJunio C Hamano <junkio@cox.net> Cc: Alan Cox <alan@lxorguk.ukuu.org.uk> Cc: Dave Jones <davej@redhat.com> Signed-off-by: NBartlomiej Zolnierkiewicz <bzolnier@gmail.com>
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- 06 7月, 2007 3 次提交
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由 Ralf Baechle 提交于
The idle loop goes to sleep using the WAIT instruction if !need_resched(). This has is suffering from from a race condition that if if just after need_resched has returned 0 an interrupt might set TIF_NEED_RESCHED but we've just completed the test so go to sleep anyway. This would be trivial to fix by just disabling interrupts during that sequence as in: local_irq_disable(); if (!need_resched()) __asm__("wait"); local_irq_enable(); but the processor architecture leaves it undefined if a processor calling WAIT with interrupts disabled will ever restart its pipeline and indeed some processors have made use of the freedom provided by the architecture definition. This has been resolved and the Config7.WII bit indicates that the use of WAIT is safe on 24K, 24KE and 34K cores. It also is safe on 74K starting revision 2.1.0 so enable the use of WAIT with interrupts disabled for 74K based on a c0_prid of at least that. Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Ralf Baechle 提交于
Older processors used to encode processor version and revision in two 4-bit bitfields, the 4K seems to simply count up and even newer MTI cores have switched to use the 8-bits as 3:3:2 bitfield with the last field as the patch number. Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Ralf Baechle 提交于
The RM7000 processors and the E9000 cores have a bug (though PMC-Sierra opposes it being called that) where invalid instructions in the same I-cache line worth of instructions being fetched may case spurious exceptions. The workaround for this was only enabled for E9000 cores; enable it also for all RM7000-based platforms. Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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