- 20 4月, 2016 1 次提交
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由 Julia Lawall 提交于
Add __init attribute on a function that is only called from other __init functions and that is not inlined, at least with gcc version 4.8.4 on an x86 machine with allyesconfig. Currently, the function is put in the .text.unlikely segment. Declaring it as __init will cause it to be put in the .init.text and to disappear after initialization. The result of objdump -x on the function before the change is as follows: 0000000000000000 l F .text.unlikely 0000000000000071 sysclk_from_fixed.constprop.5 And after the change it is as follows: 0000000000000480 l F .init.text 000000000000006c sysclk_from_fixed.constprop.5 Done with the help of Coccinelle. The semantic patch checks for local static non-init functions that are called from an __init function and are not called from any other function. Signed-off-by: NJulia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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- 16 4月, 2016 1 次提交
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由 Stephen Boyd 提交于
This flag is a no-op now. Remove usage of the flag. Cc: Hou Zhiqiang <B48286@freescale.com> Cc: Scott Wood <scottwood@freescale.com> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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- 01 12月, 2015 1 次提交
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由 Sudip Mukherjee 提交于
If get_pll_div() fails we exited by returning NULL but we missed releasing hwc. Signed-off-by: NSudip Mukherjee <sudip@vectorindia.org> Fixes: 0dfc86b3 ("clk: qoriq: Move chip-specific knowledge into driver") Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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- 27 10月, 2015 1 次提交
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由 Hou Zhiqiang 提交于
Signed-off-by: NHou Zhiqiang <B48286@freescale.com> Acked-by: NStephen Boyd <sboyd@codeaurora.org> Signed-off-by: NScott Wood <scottwood@freescale.com>
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- 23 10月, 2015 1 次提交
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由 Scott Wood 提交于
Signed-off-by: NScott Wood <scottwood@freescale.com>
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- 22 10月, 2015 2 次提交
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由 Scott Wood 提交于
LS2080A is the first implementation of the chassis 3 clockgen, which has a different register layout than previous chips. It is also little endian, unlike previous chips. Signed-off-by: NScott Wood <scottwood@freescale.com> Acked-by: NStephen Boyd <sboyd@codeaurora.org>
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由 Scott Wood 提交于
The device tree should describe the chips (or chip-like subblocks) in the system, but it generally does not describe individual registers -- it should identify, rather than describe, a programming interface. This has not been the case with the QorIQ clockgen nodes. The knowledge of what each bit setting of CLKCnCSR means is encoded in three places (binding, pll node, and mux node), and the last also needs to know which options are valid on a particular chip. All three of these locations are considered stable ABI, making it difficult to fix mistakes (of which I have found several), much less refactor the abstraction to be able to address problems, limitations, or new chips. Under the current binding, a pll clock specifier of 2 means that the PLL is divided by 4 -- and the driver implements this, unless there happen to be four clock-output-names rather than 3, in which case it interprets it as PLL divided by 3. This does not appear in the binding documentation at all. That hack is now considered stable ABI. The current device tree nodes contain errors, such as saying that T1040 can set a core clock to PLL/4 when only PLL and PLL/2 are options. The current binding also ignores some restrictions on clock selection, such as p5020's requirement that if a core uses the "wrong" PLL, that PLL must be clocked lower than the "correct" PLL and be at most 80% of the rated CPU frequency. Possibly because of the lack of the ability to express such nuance in the binding, some valid options are omitted from the device trees, such as the ability on p4080 to run cores 0-3 from PLL3 and cores 4-7 from PLL1 (again, only if they are at most 80% of rated CPU frequency). This omission, combined with excessive caution in the cpufreq driver (addressed in a subsequent patch), means that currently on a 1500 MHz p4080 with typical PLL configuration, cpufreq can lower the frequency to 1200 MHz on half the CPUs and do nothing on the others. With this patchset, all CPUs can be lowered to 1200 MHz on a rev2 p4080, and on a rev3 p4080 half can be lowered to 750 MHz and the other half to 600 MHz. The current binding only deals with CPU clocks. To describe FMan in the device tree, we need to describe its clock. Some chips have additional muxes that work like the CPU muxes, but are not described in the device tree. Others require inspecting the Reset Control Word to determine which PLL is used. Rather than continue to extend this mess, replace it. Have the driver bind to the chip-specific clockgen compatible, and keep the detailed description of quirky chip variations in the driver, where it can be easily fixed, refactored, and extended. Older device trees will continue to work (including a workaround for old ls1021a device trees that are missing compatible and reg in the clockgen node, which even the old binding required). The pll/mux details in old device trees will be ignored, but "clocks" properties pointing at the old nodes will still work, and be directed at the corresponding new clock. Signed-off-by: NScott Wood <scottwood@freescale.com> Acked-by: NStephen Boyd <sboyd@codeaurora.org>
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- 19 2月, 2015 1 次提交
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由 Emil Medve 提交于
Change-Id: Iac11ed95f274485a86d2c11f32a3dc502bcd020f Signed-off-by: NEmil Medve <Emilian.Medve@Freescale.com> Acked-by: NTang Yuantian <Yuantian.Tang@freescale.com> Signed-off-by: NMichael Turquette <mturquette@linaro.org>
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- 29 1月, 2015 7 次提交
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由 Emil Medve 提交于
Currently a mix of clk-qoriq/qoriq-clk and no prefix is used Signed-off-by: NEmil Medve <Emilian.Medve@Freescale.com> Signed-off-by: NMichael Turquette <mturquette@linaro.org>
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由 Emil Medve 提交于
Where the memset() is not necessary Signed-off-by: NEmil Medve <Emilian.Medve@Freescale.com> Signed-off-by: NMichael Turquette <mturquette@linaro.org>
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由 Emil Medve 提交于
drivers/clk/clk-qoriq.c:59:22: warning: symbol 'cmux_ops' was not declared. Should it be static? Signed-off-by: NEmil Medve <Emilian.Medve@Freescale.com> Signed-off-by: NMichael Turquette <mturquette@linaro.org>
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由 Emil Medve 提交于
WARNING:OOM_MESSAGE: Possible unnecessary 'out of memory' message + if (!parent_names) { + pr_err("%s: could not allocate parent_names\n", __func__); WARNING:OOM_MESSAGE: Possible unnecessary 'out of memory' message + if (!cmux_clk) { + pr_err("%s: could not allocate cmux_clk\n", __func__); WARNING:OOM_MESSAGE: Possible unnecessary 'out of memory' message + if (!subclks) { + pr_err("%s: could not allocate subclks\n", __func__); WARNING:OOM_MESSAGE: Possible unnecessary 'out of memory' message + if (!onecell_data) { + pr_err("%s: could not allocate onecell_data\n", __func__); Signed-off-by: NEmil Medve <Emilian.Medve@Freescale.com> Signed-off-by: NMichael Turquette <mturquette@linaro.org>
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由 Emil Medve 提交于
CHECK:ALLOC_SIZEOF_STRUCT: Prefer kzalloc(sizeof(*cmux_clk)...) over kzalloc(sizeof(struct cmux_clk)...) + cmux_clk = kzalloc(sizeof(struct cmux_clk), GFP_KERNEL); CHECK:ALLOC_SIZEOF_STRUCT: Prefer kzalloc(sizeof(*onecell_data)...) over kzalloc(sizeof(struct clk_onecell_data)...) + onecell_data = kzalloc(sizeof(struct clk_onecell_data), GFP_KERNEL); Signed-off-by: NEmil Medve <Emilian.Medve@Freescale.com> Signed-off-by: NMichael Turquette <mturquette@linaro.org>
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由 Emil Medve 提交于
WARNING:ALLOC_WITH_MULTIPLY: Prefer kcalloc over kzalloc with multiply + subclks = kzalloc(sizeof(struct clk *) * count, GFP_KERNEL); Signed-off-by: NEmil Medve <Emilian.Medve@Freescale.com> Signed-off-by: NMichael Turquette <mturquette@linaro.org>
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由 Emil Medve 提交于
CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis + rc = of_property_read_string_index(np, "clock-output-names", + 0, &clk_name); CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis + pr_err("Could not register clock provider for node:%s\n", + np->name); CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis + rc = of_property_read_string_index(np, "clock-output-names", + i, &clk_name); CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis + pr_err("Could not register clk provider for node:%s\n", + np->name); Signed-off-by: NEmil Medve <Emilian.Medve@Freescale.com> Signed-off-by: NMichael Turquette <mturquette@linaro.org>
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- 21 1月, 2015 3 次提交
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由 Tang Yuantian 提交于
Freescale introduced new ARM-based socs which using the compatible clock IP block with PowerPC-based socs'. So this driver can be used on both platforms. Updated relevant descriptions and renamed this driver to better represent its meaning and keep the function of driver untouched. Signed-off-by: NTang Yuantian <Yuantian.Tang@freescale.com> Signed-off-by: NMichael Turquette <mturquette@linaro.org>
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由 Tang Yuantian 提交于
redefine variable clocks_per_pll as a struct member If there are multiple PLL clock nodes, this variable will get overwritten. Redefining it as a struct member can avoid that. Signed-off-by: NTang Yuantian <Yuantian.Tang@freescale.com> Signed-off-by: NMichael Turquette <mturquette@linaro.org>
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由 Kevin Hao 提交于
In order to fix the following section mismatch warning: WARNING: drivers/clk/built-in.o(.data+0xe4): Section mismatch in reference from the variable ppc_corenet_clk_driver to the function .init.text:ppc_corenet_clk_probe() The variable ppc_corenet_clk_driver references the function __init ppc_corenet_clk_probe() If the reference is valid then annotate the variable with __init* or __refdata (see linux/init.h) or name the variable: *_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console WARNING: drivers/clk/built-in.o(.data+0x10c): Section mismatch in reference from the variable ppc_corenet_clk_driver to the variable .init.rodata:ppc_clk_ids The variable ppc_corenet_clk_driver references the variable __initconst ppc_clk_ids If the reference is valid then annotate the variable with __init* or __refdata (see linux/init.h) or name the variable: *_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console We can't just add the __init annotation to ppc_corenet_clk_driver or remove the __init from ppc_corenet_clk_probe() and ppc_clk_ids. So choose to use CLK_OF_DECLARE to scan and init the clock devices. Signed-off-by: NKevin Hao <haokexin@gmail.com> Acked-by: NScott Wood <scottwood@freescale.com> Acked-by: NMichael Turquette <mturquette@linaro.org> Signed-off-by: NMichael Turquette <mturquette@linaro.org>
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- 18 1月, 2015 1 次提交
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由 Kevin Hao 提交于
This reverts commit da788acb. That commit tried to fix the section mismatch warning by moving the ppc_corenet_clk_driver struct to init section. This is definitely wrong because the kernel would free the memories occupied by this struct after boot while this driver is still registered in the driver core. The kernel would panic when accessing this driver struct. Cc: stable@vger.kernel.org # 3.17 Signed-off-by: NKevin Hao <haokexin@gmail.com> Acked-by: NScott Wood <scottwood@freescale.com> Signed-off-by: NMichael Turquette <mturquette@linaro.org>
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- 20 10月, 2014 1 次提交
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由 Wolfram Sang 提交于
A platform_driver does not need to set an owner, it will be populated by the driver core. Signed-off-by: NWolfram Sang <wsa@the-dreams.de>
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- 02 7月, 2014 1 次提交
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由 Jingchang Lu 提交于
WARNING: drivers/built-in.o(.data+0x10258): Section mismatch in reference from the variable ppc_corenet_clk_driver to the (unknown reference) .init.rodata:(unknown) The variable ppc_corenet_clk_driver references the (unknown reference) __initconst (unknown) If the reference is valid then annotate the variable with __init* or __refdata (see linux/init.h) or name the variable: *_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console Signed-off-by: NJingchang Lu <jingchang.lu@freescale.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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- 20 3月, 2014 1 次提交
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由 Tang Yuantian 提交于
The clock bindings for Freescale CoreNet platform are updated. So, the driver needs to be updated accordingly. The main changes include: - Added a new node to present the input system clock - Changed PLL and MUX's compatible string Signed-off-by: NTang Yuantian <Yuantian.Tang@freescale.com> Acked-by: NScott Wood <scottwood@freescale.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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- 11 11月, 2013 1 次提交
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由 Rob Herring 提交于
Commit b5b4bb3f (of: only include prom.h on sparc) removed implicit includes of of_*.h headers by powerpc's prom.h. Some components were missed in initial clean-up patch, so add the necessary includes to fix powerpc builds. Signed-off-by: NRob Herring <rob.herring@calxeda.com> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Paul Mackerras <paulus@samba.org> Cc: Tejun Heo <tj@kernel.org> Cc: Matt Mackall <mpm@selenic.com> Cc: Herbert Xu <herbert@gondor.apana.org.au> Cc: "David S. Miller" <davem@davemloft.net> Cc: Vinod Koul <vinod.koul@intel.com> Cc: Dan Williams <dan.j.williams@intel.com> Cc: linuxppc-dev@lists.ozlabs.org Cc: linux-ide@vger.kernel.org Cc: linux-crypto@vger.kernel.org
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- 31 5月, 2013 1 次提交
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由 Tang Yuantian 提交于
The compatible string of clock is changed from *-2 to *-2.0 on chassis 2. So updated it accordingly. Signed-off-by: NTang Yuantian <Yuantian.Tang@freescale.com> Signed-off-by: NMike Turquette <mturquette@linaro.org> [mturquette@linaro.org: improved $SUBJECT line]
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- 29 5月, 2013 1 次提交
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由 Tang Yuantian 提交于
This adds the clock driver for Freescale PowerPC corenet series SoCs using common clock infrastructure. Signed-off-by: NTang Yuantian <Yuantian.Tang@freescale.com> Signed-off-by: NLi Yang <leoli@freescale.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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