- 28 7月, 2015 5 次提交
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由 Barry Song 提交于
This patch enables hardware spinlock driver for CSRatlas7 platforms. Signed-off-by: NBarry Song <Baohua.Song@csr.com>
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由 Barry Song 提交于
This patch enables RTC_CLASS and RTC driver for SiRFSoC platforms. Signed-off-by: NBarry Song <Baohua.Song@csr.com>
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由 Barry Song 提交于
we need INPUT_MISC to enable INPUT_SIRFSOC_ONKEY which is the onkey driver for SiRFSoC platforms. Signed-off-by: NBarry Song <Baohua.Song@csr.com>
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由 Barry Song 提交于
this patch enables the MMC/SDHCI driver for SiRFSoC platforms. Signed-off-by: NBarry Song <Baohua.Song@csr.com>
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由 Barry Song 提交于
this patch is againest v4.2-rc1, by doing: $ make ARCH=arm prima2_defconfig $ make ARCH=arm savedefconfig $ cp defconfig arch/arm/configs/prima2_defconfig Signed-off-by: NBarry Song <Baohua.Song@csr.com>
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- 22 7月, 2015 2 次提交
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由 Lee Jones 提交于
Signed-off-by: NLee Jones <lee.jones@linaro.org> Signed-off-by: NMaxime Coquelin <maxime.coquelin@st.com>
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由 Lee Jones 提交于
Signed-off-by: NLee Jones <lee.jones@linaro.org> Signed-off-by: NMaxime Coquelin <maxime.coquelin@st.com>
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- 17 7月, 2015 8 次提交
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由 Linus Walleij 提交于
The EP93xx SoC has a framebuffer driver, let's add this to the defconfig so we can have graphics working out of the box. Reviewed-by: NH Hartley Sweeten <hsweeten@visionengravers.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Linus Walleij 提交于
Several boards can make use of the DMA engine on the EP93xx so let's enable this by default in the defconfig. Reviewed-by: NH Hartley Sweeten <hsweeten@visionengravers.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Linus Walleij 提交于
Some of the EP93xx boards have I2C devices on bit-banged GPIO I2C, so add this to the defconfig. Reviewed-by: NH Hartley Sweeten <hsweeten@visionengravers.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Linus Walleij 提交于
The EP93xx has two designated LEDs (not always connected): a green and a red one. These are registered in the core, so let's enable the driver and some triggers. Reviewed-by: NH Hartley Sweeten <hsweeten@visionengravers.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Linus Walleij 提交于
The SIM.ONE has a MMC card connected to the SPI host. This card usually hosts an EXT4 root file system. Enable these options in the defconfig so the default ompiled kernel will work out-of-the-box. Reviewed-by: NH Hartley Sweeten <hsweeten@visionengravers.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Linus Walleij 提交于
With PATCH_PHYS_TO_VIRT we can support all EP93xx variants in a single image, so enable all board variants in the defconfig for simplicity and build coverage. Reviewed-by: NH Hartley Sweeten <hsweeten@visionengravers.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Linus Walleij 提交于
Let's set the EP93xx to NO_HZ mode and activate the high-res timers now that we have GENERIC_CLOCKEVENTS. Tested-by: NH Hartley Sweeten <hsweeten@visionengravers.com> Reviewed-by: NH Hartley Sweeten <hsweeten@visionengravers.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Magnus Damm 提交于
Now when the Marzen legacy board code is removed also get rid of the marzen_defconfig file. Existing users shall move over to shmobile_defconfig. Signed-off-by: NMagnus Damm <damm+renesas@opensource.se> Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
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- 16 7月, 2015 4 次提交
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由 Sekhar Nori 提交于
M25P80 driver provides support for most common SPI NOR devices. These devices are commonly found on TI EVMs for AM437x and DRA7x SoCs. Enable support for this driver in defconfig for omap2plus devices. Signed-off-by: NSekhar Nori <nsekhar@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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由 Sekhar Nori 提交于
CPTS module of CPSW IP enables timestamp synchronization using PTP. Enable CPTS feature of CPSW driver. Available on AM335x, AM437x and DRA7x SoCs. Signed-off-by: NSekhar Nori <nsekhar@ti.com> Acked-by: NMugunthan V N <mugunthanvnm@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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由 Sekhar Nori 提交于
Enable support for on-chip resistive touchscreen m found on AM335x and AM437x devices. Signed-off-by: NSekhar Nori <nsekhar@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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由 Sekhar Nori 提交于
Enable support for on-chip ADC found on AM335x and AM437x devices. Signed-off-by: NSekhar Nori <nsekhar@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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- 15 7月, 2015 2 次提交
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由 Kuninori Morimoto 提交于
This patch enables Renesas DPCM related sound card. It is used for... - Sampline rate convert - CTU/MIXer Note: you need to enable these settings on DTS file Signed-off-by: NKuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
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由 Kuninori Morimoto 提交于
This patch enables DPCM related sound card. It is used for... - Sampline rate convert - CTU/MIXer Note: you need to enable these settings on DTS file Signed-off-by: NKuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
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- 14 7月, 2015 2 次提交
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由 Masahiro Yamada 提交于
The UniPhier on-chip UART driver was merged into the mainline by commit 1a8d2903 ("serial: 8250_uniphier: add UniPhier serial driver"). Enable it from multi_v7_defconfig. Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: NOlof Johansson <olof@lixom.net>
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由 Baruch Siach 提交于
Signed-off-by: NBaruch Siach <baruch@tkos.co.il> Signed-off-by: NOlof Johansson <olof@lixom.net>
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- 11 7月, 2015 1 次提交
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由 John David Anglin 提交于
The increased use of pdtlb/pitlb instructions seemed to increase the frequency of random segmentation faults building packages. Further, we had a number of cases where TLB inserts would repeatedly fail and all forward progress would stop. The Haskell ghc package caused a lot of trouble in this area. The final indication of a race in pte handling was this syslog entry on sibaris (C8000): swap_free: Unused swap offset entry 00000004 BUG: Bad page map in process mysqld pte:00000100 pmd:019bbec5 addr:00000000ec464000 vm_flags:00100073 anon_vma:0000000221023828 mapping: (null) index:ec464 CPU: 1 PID: 9176 Comm: mysqld Not tainted 4.0.0-2-parisc64-smp #1 Debian 4.0.5-1 Backtrace: [<0000000040173eb0>] show_stack+0x20/0x38 [<0000000040444424>] dump_stack+0x9c/0x110 [<00000000402a0d38>] print_bad_pte+0x1a8/0x278 [<00000000402a28b8>] unmap_single_vma+0x3d8/0x770 [<00000000402a4090>] zap_page_range+0xf0/0x198 [<00000000402ba2a4>] SyS_madvise+0x404/0x8c0 Note that the pte value is 0 except for the accessed bit 0x100. This bit shouldn't be set without the present bit. It should be noted that the madvise system call is probably a trigger for many of the random segmentation faults. In looking at the kernel code, I found the following problems: 1) The pte_clear define didn't take TLB lock when clearing a pte. 2) We didn't test pte present bit inside lock in exception support. 3) The pte and tlb locks needed to merged in order to ensure consistency between page table and TLB. This also has the effect of serializing TLB broadcasts on SMP systems. The attached change implements the above and a few other tweaks to try to improve performance. Based on the timing code, TLB purges are very slow (e.g., ~ 209 cycles per page on rp3440). Thus, I think it beneficial to test the split_tlb variable to avoid duplicate purges. Probably, all PA 2.0 machines have combined TLBs. I dropped using __flush_tlb_range in flush_tlb_mm as I realized all applications and most threads have a stack size that is too large to make this useful. I added some comments to this effect. Since implementing 1 through 3, I haven't had any random segmentation faults on mx3210 (rp3440) in about one week of building code and running as a Debian buildd. Signed-off-by: NJohn David Anglin <dave.anglin@bell.net> Cc: stable@vger.kernel.org # v3.18+ Signed-off-by: NHelge Deller <deller@gmx.de>
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- 10 7月, 2015 6 次提交
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由 Mark Rutland 提交于
We currently set x27 in compat_sys_sigreturn_wrapper and compat_sys_rt_sigreturn_wrapper, similarly to what we do with r8/why on 32-bit ARM, in an attempt to prevent sigreturns from being restarted. However, on arm64 we have always used pt_regs::syscallno for syscall restarting (for both native and compat tasks), and x27 is never inspected again before being overwritten in kernel_exit. This patch removes the pointless register assignments. Signed-off-by: NMark Rutland <mark.rutland@arm.com> Cc: Will Deacon <will.deacon@arm.com> Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
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由 Ralf Baechle 提交于
We were using the native syscall and that results in subtle breakage. This is the same issue as fixed in 077d0e65 (MIPS: N32: Use compat getsockopt syscall) but that commit did fix it only for N32. Signed-off-by: NRalf Baechle <ralf@linux-mips.org> Link: https://bugzilla.kernel.org/show_bug.cgi?id=100291
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由 Paul Burton 提交于
The L2 cache in the I6400 core has 16 ways, so extend the way_string array to take such caches into account. [ralf@linux-mips.org: Other already supported CPUs are free to support more than 8 ways of cache as well.] Signed-off-by: NPaul Burton <paul.burton@imgtec.com> Signed-off-by: NMarkos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10640/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 James Hogan 提交于
Implement the mips_cdmm_phys_base() platform callback to provide a default Common Device Memory Map (CDMM) physical base address for the Pistachio SoC. This allows the CDMM in each VPE to be configured and probed for devices, such as the Fast Debug Channel (FDC). The physical address chosen is just below the default CPC address, which appears to also be unallocated. The FDC IRQ is also usable on Pistachio, and is routed through the GIC, so implement the get_c0_fdc_int() platform callback using gic_get_c0_fdc_int(), so the FDC driver doesn't have to fall back to polling. Signed-off-by: NJames Hogan <james.hogan@imgtec.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Andrew Bresticker <abrestic@chromium.org> Cc: James Hartley <james.hartley@imgtec.com> Cc: linux-mips@linux-mips.org Reviewed-by: NAndrew Bresticker <abrestic@chromium.org> Patchwork: http://patchwork.linux-mips.org/patch/9749/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 James Hogan 提交于
Wider testing reveals that the Fast Debug Channel (FDC) interrupt is routed through the GIC just fine on Pistachio SoC, even though it contains interAptiv cores. Clearly the FDC interrupt routing problems previously observed on interAptiv and proAptiv cores are specific to the Malta FPGA bitstreams. Move the workaround for interAptiv and proAptiv out of gic_get_c0_fdc_int() in the GIC irqchip driver into Malta's get_c0_fdc_int() platform callback, to allow the Pistachio SoC to use the FDC interrupt. Signed-off-by: NJames Hogan <james.hogan@imgtec.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Andrew Bresticker <abrestic@chromium.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: linux-mips@linux-mips.org Reviewed-by: NAndrew Bresticker <abrestic@chromium.org> Cc: James Hartley <james.hartley@imgtec.com> Patchwork: http://patchwork.linux-mips.org/patch/9748/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Markos Chandras 提交于
MT_SMP is not the only SMP option for MT cores. The MT_SMP option allows more than one VPE per core to appear as a secondary CPU in the system. Because of how CM works, it propagates the address-based cache ops to the secondary cores but not the index-based ones. Because of that, the code does not use IPIs to flush the L1 caches on secondary cores because the CM would have done that already. However, the CM functionality is independent of the type of SMP kernel so even in non-MT kernels, IPIs are not necessary. As a result of which, we change the conditional to depend on the CM presence. Moreover, since VPEs on the same core share the same L1 caches, there is no need to send an IPI on all of them so we calculate a suitable cpumask with only one VPE per core. Signed-off-by: NMarkos Chandras <markos.chandras@imgtec.com> Cc: <stable@vger.kernel.org> # 3.15+ Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10654/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 09 7月, 2015 10 次提交
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由 Thomas Petazzoni 提交于
The Armada 388 GP board has the following hardware features that were not enabled in mvebu_v7_defconfig: * An AT24 I2C EEPROM (also used by armada-xp-lenovo-ix4-300d) * A PCA9555 I2C GPIO expander * Several fixed regulators Therefore, this commit adds the necessary options to mvebu_v7_defconfig. Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: NGregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
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由 Markos Chandras 提交于
This reverts commit 6ca716f2. SMP/CPS is now supported on 64bit cores. Cc: <stable@vger.kernel.org> # 4.1 Reviewed-by: NPaul Burton <paul.burton@imgtec.com> Signed-off-by: NMarkos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Cc: stable@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/10592/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Markos Chandras 提交于
Replace lw/sw and various arithmetic instructions with macros so the code can work on 64-bit kernels as well. Cc: <stable@vger.kernel.org> # 3.16+ Reviewed-by: NPaul Burton <paul.burton@imgtec.com> Signed-off-by: NMarkos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Cc: stable@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/10591/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Markos Chandras 提交于
In preparation for 64-bit CPS support, we replace KSEG0 with CKSEG0 so 64-bit kernels can be supported. Cc: <stable@vger.kernel.org> # 3.16+ Reviewed-by: NPaul Burton <paul.burton@imgtec.com> Signed-off-by: NMarkos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Cc: stable@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/10590/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Markos Chandras 提交于
The cps-vec code assumes O32 ABI and uses t4-t7 in quite a few places. This breaks the build on 64-bit. As a result of which, use the pseudo-registers ta0-ta3 to make the code compatible with 64-bit. Cc: <stable@vger.kernel.org> # 3.16+ Reviewed-by: NPaul Burton <paul.burton@imgtec.com> Signed-off-by: NMarkos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Cc: stable@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/10589/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Markos Chandras 提交于
mips32r2 is a subset of mips64r2, so we replace mips32r2 with mips64r2 in preparation for 64-bit CPS support. Cc: <stable@vger.kernel.org> # 3.16+ Reviewed-by: NPaul Burton <paul.burton@imgtec.com> Signed-off-by: NMarkos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Cc: stable@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/10588/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Markos Chandras 提交于
The PTR_LA macro will pick the correct "la" or "dla" macro to load an address to a register. This gets rids of the following warnings (and others) when building a 64-bit CPS kernel: arch/mips/kernel/cps-vec.S:63: Warning: la used to load 64-bit address arch/mips/kernel/cps-vec.S:159: Warning: la used to load 64-bit address arch/mips/kernel/cps-vec.S:220: Warning: la used to load 64-bit address arch/mips/kernel/cps-vec.S:240: Warning: la used to load 64-bit address [...] Cc: <stable@vger.kernel.org> # 3.16+ Reviewed-by: NPaul Burton <paul.burton@imgtec.com> Signed-off-by: NMarkos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Cc: stable@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/10587/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Markos Chandras 提交于
Commit 1d8f1f5a ("MIPS: smp-cps: hotplug support") added hotplug support in the SMP/CPS implementation but it introduced a few build problems on 64-bit kernels due to pointer being casted to and from 'int' C types. We fix this problem by using 'unsigned long' instead which should match the size of the pointers in 32/64-bit kernels. Finally, we fix the comment since the CM base address is loaded to v1($3) instead of v0. Fixes the following build problems: arch/mips/kernel/smp-cps.c: In function 'wait_for_sibling_halt': arch/mips/kernel/smp-cps.c:366:17: error: cast from pointer to integer of different size [-Werror=pointer-to-int-cast] [...] arch/mips/kernel/smp-cps.c: In function 'cps_cpu_die': arch/mips/kernel/smp-cps.c:427:13: error: cast to pointer from integer of different size [-Werror=int-to-pointer-cast] cc1: all warnings being treated as errors Fixes: 1d8f1f5a ("MIPS: smp-cps: hotplug support") Cc: <stable@vger.kernel.org> # 3.16+ Reviewed-by: NPaul Burton <paul.burton@imgtec.com> Signed-off-by: NMarkos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Cc: stable@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/10586/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Markos Chandras 提交于
Commit 5f9f41c4 ("MIPS: kernel: Prepare the JR instruction for emulation on MIPS R6") added support for emulating the JR instruction on MIPS R6 cores but that introduced a bug which could be triggered when hitting a JALR opcode because the code used the wrong field in the 'r_format' struct to determine the instruction opcode. This lead to crashes because an emulated JALR instruction was treated as a JR one when the R6 emulator was turned off. Fixes: 5f9f41c4 ("MIPS: kernel: Prepare the JR instruction for emulation on MIPS R6") Cc: <stable@vger.kernel.org> # 4.0+ Signed-off-by: NMarkos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Cc: stable@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/10583/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Markos Chandras 提交于
Commits f1b44067 ("MIPS: Emulate the new MIPS R6 B{L,G}T{Z,}{AL,}C instructions") and commit a8ff66f5 ("MIPS: Emulate the new MIPS R6 B{L,G}E{Z,}{AL,}C instructions") added support for emulating various branch compact instructions. However, it missed the case for those which use the old BLEZL and BGTZL opcodes leading to random crashes when the R6 emulator is disabled. We fix this by ensuring that the 'rt' field is not zero which is always true for these branch compact instructions. Fixes: f1b44067 ("MIPS: Emulate the new MIPS R6 B{L,G}T{Z,}{AL,}C instructions") Fixes: a8ff66f5 ("MIPS: Emulate the new MIPS R6 B{L,G}E{Z,}{AL,}C instructions") Cc: <stable@vger.kernel.org> # 4.0+ Signed-off-by: NMarkos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Markos Chandras <markos.chandras@imgtec.com> Patchwork: https://patchwork.linux-mips.org/patch/10582/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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