Currently, edma_alloc_channel api is returning the channel
number without prepending the controller on which the
channel was allocated. So, if a channel is allocated on
2nd controller, calls subsequent to edma_alloc_channel would
never know that channel was allocated on the 2nd controller,
and continue to operate on 1st controller, resulting in edma
failure. This patch fixes this issue.
Signed-off-by: NSudhakar Rajashekhara <sudhakar.raj@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

This patch adds the CDCE949 reference oscillator to
the davinci clock list.

On the DM6467T EVM, the CDCE949 is responsible for
generating the pixel clock for display. On the DM6467
EVM, this pixel clock was being obtained from an
internal source. This is not possible on the DM6467T
EVM because of the presence of a 33MHz oscillator.

The TSIF module also requires the CDCE949 to generate
the data clocks.

The actual clock definitions will be added by patches
adding support for DM6467T VPIF and TSIF. This patch
mearly lays the foundation for that work.
Signed-off-by: NNageswari Srinivasan <nageswari@ti.com>
Signed-off-by: NSekhar Nori <nsekhar@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

This patch adds support for TI's CDCE949 - a clock
synthesizer with 4 PLLs and 9 outputs.

It is used on DM6467 EVM. On the EVM, it generates
clocks required for VPIF, TSIF and Audio modules.

This patch adds it as part of the DaVinci clock framework.

Testing:
The various frequency outputs on Y1 have been tested using
a out-of-tree VPIF video driver supporting HD video.
The register values for Y5 frequency outputs have been
derived from TSIF driver sources in MontaVista LSP kernel,
but actual output has not been tested for lack of TSIF
driver which actually works on the latest kernel.
Signed-off-by: NNageswari Srinivasan <nageswari@ti.com>
Signed-off-by: NSekhar Nori <nsekhar@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

Signed-off-by: NSekhar Nori <nsekhar@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

This patch adds support for registering for suspend-to-RAM
functionality on da850/omap-l138 SoCs.

da850 supports wakeup based on external event and RTC
alarm.

Currently only RTC alarm based wakeup is supported.
Support for wakeup based on external event will be
added as later improvements.

For scheduling an alarm event on RTC some useful code
is present in Documentation/rtc.txt
Signed-off-by: NSekhar Nori <nsekhar@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

This patch adds core power management (suspend-to-RAM)
support for DaVinci SoCs.

The code depends on the the "deepsleep" feature to suspend
the SoC and saves power by gating the input clock.

The wakeup can be based on an external event as supported
by the SoC.

Assembly code (in sleep.S) is added to aid gating DDR2
clocks. Code doing this work should not be accessing DDR2.
The assembly code is relocated to SRAM by the code in pm.c

The support has been validated on DA850/OMAP-L138 only
though the code is (hopefully) generic enough that other
SoCs supporting deepsleep feature simply requires SoC
specific code to start using this driver.

Note that all the device drivers don't support suspend/resume
still and are being worked on.
Signed-off-by: NSekhar Nori <nsekhar@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

In DM365 Q0, Q1 and Q2 are used by codecs.
LSP drivers should use Q3.
This patch changes the default queue for DM365.
Signed-off-by: NSandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

Some modules do not have PSC to control their clocks.
The 'lpsc' field in the clk structure is 0 for such clocks.

In the clock disable function check for CLK PSC flag before
disabling the PSC. If this is not taken care of then it may
so happen that module controlled by LPSC 0 is erroneously disabled.
Signed-off-by: NChaithrika U S <chaithrika@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

The davinci EMAC peripheral is also available on other TI
platforms -notably TI AM3517 SoC. This patch modifies the
config option and the platform structure header files so that
the driver can be reused on non-davinci platforms as well.
Signed-off-by: NSriramakrishnan <srk@ti.com>
Acked-by: NChaithrika U S <chaithrika@ti.com>
Acked-by: NDavid S. Miller <davem@davemloft.net>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

This patch initializes the platform data to enable 4-bit
ecc support on DA850/OMAP-L138.
Signed-off-by: NSudhakar Rajashekhara <sudhakar.raj@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

On DA850/OMAP-L138, NOR flash partition was starting from offset
ZERO erasing the UBL and u-boot when the complete NOR is erased.
This patch moves the start of the partition to 512K, after the
bootloaders and u-boot env variables.

This patch also creates a new partition on NOR Flash to store
Linux kernel image.
Signed-off-by: NSudhakar Rajashekhara <sudhakar.raj@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

Move /proc/davinci_clocks to /sys/kernel/debug/davinci_clocks
(debugfs).

debugfs is more suited for this since the clock dump is
debug information.
Signed-off-by: NSekhar Nori <nsekhar@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

This patch modifies clock dump to take care of
clock tress rooted at multiple oscillators.
Current code assumes the entire tree is rooted
on a single oscillator. When using off-chip
clock synthesizers, some of the clocks can
be obtained from a different on-board oscillator.
Signed-off-by: NSekhar Nori <nsekhar@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

DM6467T (T for Turbo) is a newer and faster DM6467
part from TI. The new part supports 1080p video and
has the ARM running at 495MHz. More SoC information:

http://focus.ti.com/docs/prod/folders/print/tms320dm6467t.html

Spectrum Digital, Inc has a new EVM for this part.
It is _mostly_ same as the older DM6467 EVM except
for a 33MHz crystal input and THS8200 video encoder
for 1080p support.

The meat of this patch is dedicated to initializing
the crystal frequency from EVM board file.

Additional notes:
I did consider some alternative ways to make the crystal
input board specific including - (1) having board code
initialize the crystal frequency using the first member
of soc_info->cpu_clks array (2) introducing a new ref_clk_rate
member in soc_info structure.

But, the current way seems to be the simplest and least
intruding considering that both the clock array and SoC
info structure are actually private to the SoC file. Also
the fact that davinci_common_init() initializes both the
soc_info and clocks in one go.
Signed-off-by: NSekhar Nori <nsekhar@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

Currently all the #defines and static variables in the
board-dm646x-evm.c file are located right at the start
of the file because of which the related code is not
together - making reading the code difficult.

This patch moves around the code keeping related code
together.
Signed-off-by: NSekhar Nori <nsekhar@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

Leave a comment explaining the constant value of 27Mhz used
in include/mach/timex.h for all DaVinci platforms. Many of
the platforms actually run at 24MHz timer frequency (Eg.
EVMs of DM355, DM365 and OMAP-L1).

The comment also serves as a porting alert.
Signed-off-by: NSekhar Nori <nsekhar@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

Create static map for internal SRAM and populate SRAM base
and size in soc_info structure to allow SRAM allocation
functions from arch/arm/mach-davinci/sram.c to work.

On DA850 SRAM is used for suspend-to-RAM implementation
in places where DDR2 cannot be accessed as its clocks are
stopped.
Signed-off-by: NSekhar Nori <nsekhar@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

On omap-l1 devices the PLL registers can be locked from
writes. Currently the cpufreq rate setting code unlocks
PLL0 before the write actually happens. With suspend
support getting added PLL1 registers need be be unlocked
as well.

To facilitate this, unlock both PLLs during the init time
itself.

This also obviates the need to unlock PLL registers for
each CPUFreq transtition.
Signed-off-by: NSekhar Nori <nsekhar@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

When suspend is supported, both cpuidle and suspend code
need to work on DDR2 registers. Instead of mapping the
DDR2 registers twice, do it once outside of cpuidle
driver and let cpuidle driver get the virtual base address
of DDR2 registers.
Signed-off-by: NSekhar Nori <nsekhar@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

psc.h contains register defines for PSC module which
need to be accessed in assembly code which helps the
DA850/OMAP-L138 SoC go to sleep. Shutting down DDR clock
using PSC is a part of the sleep procedure.

Also, the PLL related hardware definitions in clock.h are
needed in assembly code to bypass the DDR2 PLL.
Signed-off-by: NSekhar Nori <nsekhar@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

The motivation behind the change is to use the same
definitions in the assembly code responsible for
suspending the SoC, a part of which is to clock gate
the DDR2 clock.

Note that the assembly code cannot invoke the C function
meant for this. The main reason being that stack in DDR2
cannot be accessed while DDR2 clock is being clock gated.
Signed-off-by: NSekhar Nori <nsekhar@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

Move defintions of DDR2 controller registers to memory.h
from cpuidle.c. The motivation behind the change is to be
able to use these defintions in assembly code that puts
DDR2 in self-refresh and enables the SoC to enter suspend
state.
Signed-off-by: NSekhar Nori <nsekhar@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

As suspend support is added, the code supporting
the suspend operation needs to bypass PLLs and
needs to access the same wait time values as the
PLL code in clock.c.

To facilitate this, move the PLL wait times to
clock.h where they can be accessed by suspend code.
Signed-off-by: NSekhar Nori <nsekhar@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

OMAP-L138 adds a second SYSCFG region having useful functionality
like deep sleep, pull up/down control and SATA clock stop.

This patch makes provision for accessing registers from second
SYSCFG region in da8xx code.

Note that OMAP-L137 has a single SYSCFG region.
Signed-off-by: NSekhar Nori <nsekhar@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

This patch adds following changes:-
	1) add sub device configuration data for TVP5146 used by vpfe capture
	2) registers platform devices for vpfe_capture, isif and vpss
	3) defines hardware resources for the devices listed under 2)
	4) defines clock aliase for isif driver
	5) adding setup_pinmux() for isif
Signed-off-by: NMurali Karicheri <m-karicheri2@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

This patch fixes power LED blinking and power-off on DNS-323 rev. B1.

GPIO pin 3 has to be set to 1 to stop power LED blinking and to allow the LED to be controlled via leds-gpio. This pin has to be also set to 1 for power-off to work.
To power-off the rev. B1 machine, pin 8 has to be set to 1 and then set to 0 to do actual power-off.

Tested on my DNS-323 rev. B1
Signed-off-by: NErik Benada <erikbenada@yahoo.ca>
Signed-off-by: NNicolas Pitre <nico@marvell.com>

OMAP GP timers keep running for a few cycles after they are stopped,
which can cause the timer to expire and generate an interrupt. The
pending interrupt will prevent e.g. OMAP from entering suspend, thus
we ack it manually.  Only applicable on OMAP2/3/4.
Signed-off-by: NTero Kristo <tero.kristo@nokia.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Commit cfc38999f (backlight: Pass device through notify callback)
added a struct device argument to the notify callback, but didn't
update the user of it in mach-hmt.c
Signed-off-by: NPeter Korsgaard <jacmet@sunsite.dk>
Signed-off-by: NBen Dooks <ben-linux@fluff.org>

Fix following warning when CONFIG_DEBUG_FS wasn't selected:

arch/arm/mach-omap2/pm-debug.c:57: warning: 'pm_dbg_init' declared 'static' but never defined
Signed-off-by: NSergio Aguirre <saaguirre@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

Currently, DSS does not wakeup when there is a DMA request.  DSS wake
up event must be enabled so that the DMA request to refill the FIFO
will wake up the CORE domain.
Signed-off-by: NSubramani Venkatesh <subramani.venkatesh@windriver.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

During suspend, the kernel timekeeping subsystem is shut down.  Before
suspend and upon resume, it uses a weak function
read_persistent_clock() to determine the amount of time that elapsed
during suspend.

This function was not implemented on OMAP, so from the timekeeping
subsystem perspective (and thus userspace as well) it appeared that no
time elapsed during suspend.

This patch uses the 32k sync timer as a the persistent clock.

NOTE: This does *NOT* fully handle wrapping of the 32k sync timer, so
      more than one wrapping of the 32k sync timer during suspend may
      cause problems.  Also note there are not interrupts when the 32k
      sync timer wraps, so something else has to be done.
Reported-by: NJon Hunter <jon-hunter@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

Due to OMAP3 erratas 1.157, 1.185 the save of the last pad register
(ETK_D14 and ETK_D15) can fail sometimes when there is simultaneous
OCP access to the SCM register area. Fixed by writing the last
register to the save area.

Also, optimized the delay loop for the HW save to include an udelay(1),
which limits the number of unnecessary HW accesses to SCM register area
during the save.
Signed-off-by: NTero Kristo <tero.kristo@nokia.com>
Acked-by: NNishanth Menon <nm@ti.com>
Reviewed-by: NAnand Gadiyar <gadiyar@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

val is an u64 pointer, we need an int to check the error.
Signed-off-by: NRoel Kluin <roel.kluin@gmail.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

Wake-up from McBSP ports are needed, especially when the THRESHOLD
dma mode is in use for audio playback.
Signed-off-by: NPeter Ujfalusi <peter.ujfalusi@nokia.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

The PM debug code fails to build on when CONFIG_DEBUG_FS is not
enabled.

Build error log:
arch/arm/mach-omap2/built-in.o: In function `omap_sram_idle':
arch/arm/mach-omap2/pm34xx.c:449: undefined reference to `pm_dbg_regset_save'
arch/arm/mach-omap2/pm34xx.c:460: undefined reference to `pm_dbg_regset_save'
arch/arm/mach-omap2/built-in.o: In function `configure_vc':
arch/arm/mach-omap2/pm34xx.c:1237: undefined reference to `pm_dbg_regset_init'
arch/arm/mach-omap2/pm34xx.c:1238: undefined reference to `pm_dbg_regset_init'
make: *** [.tmp_vmlinux1] Error 1

This patch fixes the above errors.

Kernel booting is tested on omap zoom2 and zoom3 boards.
Signed-off-by: NManjunatha GK <manjugk@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

As part of Core domain context restoration while coming out of off mode
there are some registers being restored which are not required to be restored.
ROM code will have restored them already. Overwriting some of them can have
potential side effect. Eg: CM_CLKEN_PLL register should not be written while dpll is locked.
Tested on OMAP 3430 SDP for suspend/resume and off mode with sleep_while_idle enabled.
Signed-off-by: NVishwanath BS <vishwanath.bs@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

Current value is stored on SDRAM and it is written back during wakeup.
Previously a static value of 0x72 was written there.
Signed-off-by: NTero Kristo <tero.kristo@nokia.com>
Acked-by: NThara Gopinath <thara@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

Previously used u32 as temporary data storage that wraps around at 4.294s.
Signed-off-by: NTero Kristo <tero.kristo@nokia.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

This patch removes code blocks that are repeated
in function prcm_setup_regs().
Signed-off-by: NSanjeev Premi <premi@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>