1. 02 3月, 2010 13 次提交
  2. 24 2月, 2010 5 次提交
  3. 20 2月, 2010 2 次提交
  4. 19 2月, 2010 2 次提交
  5. 18 2月, 2010 1 次提交
  6. 17 2月, 2010 2 次提交
  7. 16 2月, 2010 1 次提交
  8. 15 2月, 2010 1 次提交
    • P
      sh64: fix tracing of signals. · 4b505db9
      Paul Mundt 提交于
      This follows the parisc change to ensure that tracehook_signal_handler()
      is aware of when we are single-stepping in order to ptrace_notify()
      appropriately. While this was implemented for 32-bit SH, sh64 neglected
      to make use of TIF_SINGLESTEP when it was folded in with the 32-bit code,
      resulting in ptrace_notify() never being called.
      
      As sh64 uses all of the other abstractions already, this simply plugs in
      the thread flag in the appropriate enable/disable paths and fixes up the
      tracehook notification accordingly. With this in place, sh64 is brought
      in line with what 32-bit is already doing.
      Reported-by: NMike Frysinger <vapier@gentoo.org>
      Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
      4b505db9
  9. 14 2月, 2010 2 次提交
    • P
      powerpc/85xx: Fix SMP when "cpu-release-addr" is in lowmem · d1d47ec6
      Peter Tyser 提交于
      Recent U-Boot commit 5ccd29c3679b3669b0bde5c501c1aa0f325a7acb caused
      the "cpu-release-addr" device tree property to contain the physical RAM
      location that secondary cores were spinning at.  Previously, the
      "cpu-release-addr" property contained a value referencing the boot page
      translation address range of 0xfffffxxx, which then indirectly accessed
      RAM.
      
      The "cpu-release-addr" is currently ioremapped and the secondary cores
      kicked.  However, due to the recent change in "cpu-release-addr", it
      sometimes points to a memory location in low memory that cannot be
      ioremapped.  For example on a P2020-based board with 512MB of RAM the
      following error occurs on bootup:
      
        <...>
        mpic: requesting IPIs ...
        __ioremap(): phys addr 0x1ffff000 is RAM lr c05df9a0
        Unable to handle kernel paging request for data at address 0x00000014
        Faulting instruction address: 0xc05df9b0
        Oops: Kernel access of bad area, sig: 11 [#1]
        SMP NR_CPUS=2 P2020 RDB
        Modules linked in:
        <... eventual kernel panic>
      
      Adding logic to conditionally ioremap or access memory directly resolves
      the issue.
      Signed-off-by: NPeter Tyser <ptyser@xes-inc.com>
      Signed-off-by: NNate Case <ncase@xes-inc.com>
      Reported-by: NDipen Dudhat <B09055@freescale.com>
      Tested-by: NDipen Dudhat <B09055@freescale.com>
      Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
      d1d47ec6
    • A
      powerpc/85xx: Fix oops during MSI driver probe on MPC85xxMDS boards · fa644298
      Anton Vorontsov 提交于
      MPC85xx chips report the wrong value in feature reporting register,
      and that causes the following oops:
      
       Unable to handle kernel paging request for data at address 0x00000c00
       Faulting instruction address: 0xc0019294
       Oops: Kernel access of bad area, sig: 11 [#1]
       MPC8569 MDS
       Modules linked in:
       [...]
       NIP [c0019294] mpic_set_irq_type+0x2f0/0x368
       LR [c0019124] mpic_set_irq_type+0x180/0x368
       Call Trace:
       [ef851d60] [c0019124] mpic_set_irq_type+0x180/0x368 (unreliable)
       [ef851d90] [c007958c] __irq_set_trigger+0x44/0xd4
       [ef851db0] [c007b550] set_irq_type+0x40/0x7c
       [ef851dc0] [c0004a60] irq_create_of_mapping+0xb4/0x114
       [ef851df0] [c0004af0] irq_of_parse_and_map+0x30/0x40
       [ef851e20] [c0405678] fsl_of_msi_probe+0x1a0/0x328
       [ef851e60] [c02e6438] of_platform_device_probe+0x5c/0x84
       [...]
      
      This is because mpic_alloc() assigns wrong values to
      mpic->isu_{size,shift,mask}, and things eventually break when
      _mpic_irq_read() is trying to use them.
      
      This patch fixes the issue by enabling MPIC_BROKEN_FRR_NIRQS quirk.
      Signed-off-by: NAnton Vorontsov <avorontsov@ru.mvista.com>
      Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
      fa644298
  10. 13 2月, 2010 2 次提交
  11. 12 2月, 2010 1 次提交
  12. 11 2月, 2010 7 次提交
  13. 10 2月, 2010 1 次提交
    • S
      x86, apic: Don't use logical-flat mode when CPU hotplug may exceed 8 CPUs · 681ee44d
      Suresh Siddha 提交于
      We need to fall back from logical-flat APIC mode to physical-flat mode
      when we have more than 8 CPUs.  However, in the presence of CPU
      hotplug(with bios listing not enabled but possible cpus as disabled cpus in
      MADT), we have to consider the number of possible CPUs rather than
      the number of current CPUs; otherwise we may cross the 8-CPU boundary
      when CPUs are added later.
      
      32bit apic code can use more cleanups (like the removal of vendor checks in
      32bit default_setup_apic_routing()) and more unifications with 64bit code.
      Yinghai has some patches in works already. This patch addresses the boot issue
      that is reported in the virtualization guest context.
      
      [ hpa: incorporated function annotation feedback from Yinghai Lu ]
      Signed-off-by: NSuresh Siddha <suresh.b.siddha@intel.com>
      LKML-Reference: <1265767304.2833.19.camel@sbs-t61.sc.intel.com>
      Acked-by: NShaohui Zheng <shaohui.zheng@intel.com>
      Reviewed-by: NYinghai Lu <yinghai@kernel.org>
      Cc: <stable@kernel.org>
      Signed-off-by: NH. Peter Anvin <hpa@zytor.com>
      681ee44d