- 22 6月, 2015 5 次提交
-
-
由 Vineet Gupta 提交于
Reported by Anton as LTP:munmap01 failing with Illegal Instruction Exception. --------------------->8-------------------------------------- mmap2(NULL, 24576, PROT_READ|PROT_WRITE, MAP_SHARED, 3, 0) = 0x200d2000 munmap(0x200d2000, 24576) = 0 --- SIGSEGV {si_signo=SIGSEGV, si_code=SEGV_MAPERR, si_addr=0x200d2000} --- potentially unexpected fatal signal 4. Path: /munmap01 CPU: 0 PID: 61 Comm: munmap01 Not tainted 3.13.0-g5d5c46d9a556 #8 task: 9f1a8000 ti: 9f154000 task.ti: 9f154000 [ECR ]: 0x00020100 => Illegal Insn [EFA ]: 0x0001354c [BLINK ]: 0x200515d4 [ERET ]: 0x1354c @off 0x1354c in [/munmap01] VMA: 0x00010000 to 0x00018000 [STAT32]: 0x800802c0 ... --------------------->8-------------------------------------- The issue was 1. munmap01 accessed unmapped memory (on purpose) with signal handler installed for SIGSEGV 2. The faulting instruction happened to be in Delay Slot 00011864 <main>: 11908: bl.d 13284 <tst_resm> 1190c: stb r16,[r2] 3. kernel sets up the reg file for signal handler and correctly clears the DE bit in pt_regs->status32 placeholder 4. However RESTORE_CALLEE_SAVED_USER macro is not adjusted for ARCv2, and it over-writes the above with orig/stale value of status32 5. After RTIE, userspace signal handler executes a non branch instruction with DE bit set, triggering Illegal Instruction Exception. Reported-by: NAnton Kolesov <akolesov@synopsys.com> Signed-off-by: NVineet Gupta <vgupta@synopsys.com> -
由 Vineet Gupta 提交于
Signed-off-by: NVineet Gupta <vgupta@synopsys.com> -
由 Vineet Gupta 提交于
The notable features are: - SMP configurations of upto 4 cores with coherency - Optional L2 Cache and IO-Coherency - Revised Interrupt Architecture (multiple priorites, reg banks, auto stack switch, auto regfile save/restore) - MMUv4 (PIPT dcache, Huge Pages) - Instructions for * 64bit load/store: LDD, STD * Hardware assisted divide/remainder: DIV, REM * Function prologue/epilogue: ENTER_S, LEAVE_S * IRQ enable/disable: CLRI, SETI * pop count: FFS, FLS * SETcc, BMSKN, XBFU... Signed-off-by: NVineet Gupta <vgupta@synopsys.com> -
由 Vineet Gupta 提交于
Cc: Jason Cooper <jason@lakedaemon.net> Cc: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: NVineet Gupta <vgupta@synopsys.com> -
由 Vineet Gupta 提交于
ioremap already uses the hard define, just make sure BCR value matches that Signed-off-by: NVineet Gupta <vgupta@synopsys.com>
-
- 19 6月, 2015 35 次提交
-
-
由 Vineet Gupta 提交于
Signed-off-by: NVineet Gupta <vgupta@synopsys.com> -
由 Vineet Gupta 提交于
These have been register compatible so far. However ARCv2 mandates different pt_regs layout (due to h/w auto save). To keep pt_regs same for both, we start by removing the assumption - used mainly for block copies between the 2 structs in signal handling and ptrace Signed-off-by: NVineet Gupta <vgupta@synopsys.com> -
由 Vineet Gupta 提交于
Previously this macro was overloaded with stack switching, saving SP at right slot in pt_regs, saving/setup of r25 and setting SP baseline to where pt_regs->sp is saved (vs. bottom of pt_regs) Now it only does SP switch, and leaves SP pointing to bottom of pt_regs. r25 saving is no longer done here to allow for future reordering of regfile in pt_regs w/o touching this macro Signed-off-by: NVineet Gupta <vgupta@synopsys.com> -
由 Vineet Gupta 提交于
Returning from pure kernel mode and exception mode use the same code anyways. Remove one the duplicate blocks Signed-off-by: NVineet Gupta <vgupta@synopsys.com> -
由 Vineet Gupta 提交于
Elide the need to re-read ECR in Trap handler by ensuring that EXCEPTION_PROLOGUE does that at the very end just before returning to Trap handler ARCv2 EXCEPTION_PROLOGUE already did that, so same for ARcompact and the common trap handler adjusted to use cached ECR Signed-off-by: NVineet Gupta <vgupta@synopsys.com> -
由 Vineet Gupta 提交于
Signed-off-by: NVineet Gupta <vgupta@synopsys.com> -
由 Vineet Gupta 提交于
Signed-off-by: NVineet Gupta <vgupta@synopsys.com> -
由 Vineet Gupta 提交于
This fixes the possible link/relo errors, since restore_regs will be provided by ISA code, but called from ARC common code. The .L prefix reassures binutils that it will be in same compilation unit. Signed-off-by: NVineet Gupta <vgupta@synopsys.com> -
由 Vineet Gupta 提交于
Signed-off-by: NVineet Gupta <vgupta@synopsys.com> -
由 Vineet Gupta 提交于
Signed-off-by: NVineet Gupta <vgupta@synopsys.com> -
由 Vineet Gupta 提交于
Signed-off-by: NVineet Gupta <vgupta@synopsys.com> -
由 Vineet Gupta 提交于
Signed-off-by: NVineet Gupta <vgupta@synopsys.com> -
由 Vineet Gupta 提交于
-EXCEPTION_EPILOGUE introduced -EXCEPTION_PROLOGUE now also includes reg file saving Signed-off-by: NVineet Gupta <vgupta@synopsys.com> -
由 Vineet Gupta 提交于
-common'ize macros for level 1 and level 2 interrupts Signed-off-by: NVineet Gupta <vgupta@synopsys.com> -
由 Vineet Gupta 提交于
Signed-off-by: NVineet Gupta <vgupta@synopsys.com> -
由 Vineet Gupta 提交于
- Remove the ifdef'ery and write distinct versions for each mmu ver even if there is some code duplication Signed-off-by: NVineet Gupta <vgupta@synopsys.com> -
由 Vineet Gupta 提交于
That is because __after_dc_op() already reads it for status check, so it is better anyways to use that "newer" value. Also reduces the clutter in callers for passing from/to these routines. Signed-off-by: NVineet Gupta <vgupta@synopsys.com> -
由 Vineet Gupta 提交于
Signed-off-by: NVineet Gupta <vgupta@synopsys.com> -
由 Vineet Gupta 提交于
Signed-off-by: NVineet Gupta <vgupta@synopsys.com> -
由 Vineet Gupta 提交于
Signed-off-by: NVineet Gupta <vgupta@synopsys.com> -
由 Alexey Brodkin 提交于
As DW Mobile Storage databook says it's required to use "Hold Register" if card is enumerated in SDR12 or SDR25 modes. It means we need to act in the same way as in Altera's Socfpga implementation - set "use hold reg" bit in commad. Note that for upstream proper solution would be to remove dw_mci_pltfm_prepare_command() at all and set the bit right in dw_mci_prepare_command() for all platforms. Signed-off-by: NAlexey Brodkin <abrodkin@synopsys.com> Signed-off-by: NVineet Gupta <vgupta@synopsys.com>
-
由 Vineet Gupta 提交于
Route all MB originated traffic to DDR Port 1 and keep Port 0 for CPU traffic only Basic system parameters -------------------------------------------------------------------------------------- Host OS Description Mhz tlb cache mem scal pages line par load bytes ----------------- ------------- --------------------------------------- ---- ----- ----- ------ ---- axs101-sd-2-new-f Linux 3.13.0+ axs101-sd-2-new-fw-old-img-rerun 739 8 32 1.1100 1 axs101-sd-3-arc-3 Linux 3.13.9+ axs101-sd-3-arc-3.13-tip-regression 735 8 32 1.1000 1 axs101-sd-9-diffe Linux 3.13.11 axs101-sd-9-different-tweak 740 8 32 1.0000 1 Processor, Processes - times in microseconds - smaller is better ------------------------------------------------------------------------------ Host OS Mhz null null open slct sig sig fork exec sh call I/O stat clos TCP inst hndl proc proc proc --------- ------------- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- axs101-sd Linux 3.13.0+ 739 0.50 0.88 5.38 14.6 34.1 0.92 5.18 2135 6555 12.K axs101-sd Linux 3.13.9+ 735 0.50 0.90 5.89 19.2 81.4 0.94 4.08 2560 8559 15.K axs101-sd Linux 3.13.11 740 0.50 0.88 4.45 17.8 34.4 0.94 3.25 2052 6493 12.K ^^^^ ^^^^ Signed-off-by: NVineet Gupta <vgupta@synopsys.com> -
由 Vineet Gupta 提交于
Earlycon calculates UART clock as "BASE_BAUD * 16". In case of ARC "BASE_BAUD" is calculated dynamically in runtime, basically it is an alias to arc_early_base_baud(), which in turn just does "arc_base_baud/16". 8250 UART on AXS/SDP board uses 33.3MHz clock source which is set in "arc_base_baud" with this change. Additional compatibility string "snps,arc-sdp" is introduced as well because there're different flavours of AXS boards but they all share the same motherboard and so it's possible to re-use the same code for motherbord even if CPU daughterboard changes. Signed-off-by: NVineet Gupta <vgupta@synopsys.com> -
由 Alexey Brodkin 提交于
The AXS10x platforms consist of a mainboard with peripherals, on which several daughter cards can be placed. The daughter cards typically contain a CPU and memory. Signed-off-by: NMischa Jonker <mjonker@synopsys.com> Signed-off-by: NAlexey Brodkin <abrodkin@synopsys.com> Signed-off-by: NVineet Gupta <vgupta@synopsys.com>
-
由 Vineet Gupta 提交于
Signed-off-by: NVineet Gupta <vgupta@synopsys.com> -
由 Vineet Gupta 提交于
Currently, it doesn't invoke the callback but continues to unwind Also while at it - simplify the code a bit Signed-off-by: NVineet Gupta <vgupta@synopsys.com> -
由 Tobias Klauser 提交于
Directly return the result of perf_pmu_register() in arc_pmu_device_probe() instead of assigning and returning variable ret. Signed-off-by: NTobias Klauser <tklauser@distanz.ch> Signed-off-by: NVineet Gupta <vgupta@synopsys.com>
-
由 Max Filippov 提交于
static arc_pmu in the arch/arc/kernel/perf_event.c is not initialized as it's shadowed by a local variable of the same name in the arc_pmu_device_probe. Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com> Fixes: 03c94fcf "ARC: perf: make @arc_pmu static global" CC: <stable@vger.kernel.org> # 4.1 Signed-off-by: NVineet Gupta <vgupta@synopsys.com>
-
由 Vineet Gupta 提交于
Signed-off-by: NVineet Gupta <vgupta@synopsys.com> -
由 Vineet Gupta 提交于
Signed-off-by: NVineet Gupta <vgupta@synopsys.com> -
由 Vineet Gupta 提交于
* Remove remanants of legacy ARC FPGA platforms (AA4, ML509...) * Only nsim simulation platform is left, rename platform accordingly * AA4 DT stuff is compatible with nsim for ARC700 so rename it too Signed-off-by: NVineet Gupta <vgupta@synopsys.com> -
由 Vineet Gupta 提交于
With ISS long unsupported, no point in having extension based on it Signed-off-by: NVineet Gupta <vgupta@synopsys.com> -
由 Vineet Gupta 提交于
Signed-off-by: NVineet Gupta <vgupta@synopsys.com> -
由 Vineet Gupta 提交于
Signed-off-by: NVineet Gupta <vgupta@synopsys.com> -
由 Vineet Gupta 提交于
Signed-off-by: NVineet Gupta <vgupta@synopsys.com>
-