- 11 6月, 2013 1 次提交
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由 Ralf Baechle 提交于
This enables support for CONFIG_NO_HZ_FULL. Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 23 5月, 2013 1 次提交
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由 David Daney 提交于
In C, one definition is sufficient. Signed-off-by: NDavid Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5304/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 17 5月, 2013 2 次提交
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由 David Daney 提交于
This reverts commit d532f3d2. The original commit has several problems: 1) Doesn't work with 64-bit kernels. 2) Calls TLBMISS_HANDLER_SETUP() before the code is generated. 3) Calls TLBMISS_HANDLER_SETUP() twice in per_cpu_trap_init() when only one call is needed. [ralf@linux-mips.org: Also revert the bits of the ASID patch which were hidden in the KVM merge.] Signed-off-by: NDavid Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: "Steven J. Hill" <Steven.Hill@imgtec.com> Cc: David Daney <david.daney@cavium.com> Patchwork: https://patchwork.linux-mips.org/patch/5242/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 David Daney 提交于
This reverts commit f6b06d93. The next revert depends on this one, so this has to go too. Signed-off-by: NDavid Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: "Steven J. Hill" <Steven.Hill@imgtec.com> Cc: David Daney <david.daney@cavium.com> Patchwork: https://patchwork.linux-mips.org/patch/5241/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 09 5月, 2013 3 次提交
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由 Steven J. Hill 提交于
All exceptions must be taken in microMIPS mode, never in classic MIPS mode or the kernel falls apart. A few NOP instructions are used to maintain the correct alignment of microMIPS versions of the exception vectors. Signed-off-by: NSteven J. Hill <Steven.Hill@imgtec.com>
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由 Steven J. Hill 提交于
The macros did not properly take into account the ISA that the kernel was being compiled with. A classic MIPS kernel will have the standard 'uasm_i_##op' macro functions with 'MM_uasm_i_##op' macro functions for the microMIPS version. A pure microMIPS kernel will have the standard macros with 'CL_uasm_i_##op' macro functions for the classic version. Signed-off-by: NSteven J. Hill <Steven.Hill@imgtec.com>
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由 Steven J. Hill 提交于
Jump or branch target addresses have the first bit set. The original mask did not take this into account and will cause a field overflow warning for the target address when a jump immediate instruction is built. Signed-off-by: NSteven J. Hill <Steven.Hill@imgtec.com>
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- 08 5月, 2013 4 次提交
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由 Steven J. Hill 提交于
Changes for pure microMIPS cores to dynamically determine the ASID size at boot time. Includes bug fix https://patchwork.linux-mips.org/patch/5230/Signed-off-by: NSteven J. Hill <Steven.Hill@imgtec.com> Signed-off-by: NJonas Gorski <jogo@openwrt.org>
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由 Steven J. Hill 提交于
Original patch by Ralf Baechle and removed by Harold Koerfgen with commit f67e4ffc79905482c3b9b8c8dd65197bac7eb508. This allows for more generic kernels since the size of the ASID and corresponding masks can be determined at run-time. This patch is also required for the new Aptiv cores and has been tested on Malta and Malta Aptiv platforms. [ralf@linux-mips.org: Added relevant part of fix https://patchwork.linux-mips.org/patch/5213/] Signed-off-by: NSteven J. Hill <Steven.Hill@imgtec.com> Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Sanjay Lal 提交于
Signed-off-by: NSanjay Lal <sanjayl@kymasys.com> Cc: kvm@vger.kernel.org Cc: linux-mips@linux-mips.org Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Huacai Chen 提交于
This and the next patch resolve memory corruption problems while CPU hotplug. Without these patches, memory corruption can triggered easily as below: On a quad-core MIPS platform, use "spawn" of UnixBench-5.1.3 (http:// code.google.com/p/byte-unixbench/) and a CPU hotplug script like this (hotplug.sh): while true; do echo 0 >/sys/devices/system/cpu/cpu1/online echo 0 >/sys/devices/system/cpu/cpu2/online echo 0 >/sys/devices/system/cpu/cpu3/online sleep 1 echo 1 >/sys/devices/system/cpu/cpu1/online echo 1 >/sys/devices/system/cpu/cpu2/online echo 1 >/sys/devices/system/cpu/cpu3/online sleep 1 done Run "hotplug.sh" and then run "spawn 10000", spawn will get segfault after a few minutes. This patch: Currently, clear_page()/copy_page() are generated by Micro-assembler dynamically. But they are unavailable until uasm_resolve_relocs() has finished because jump labels are illegal before that. Since these functions are shared by every CPU, we only call build_clear_page()/ build_copy_page() only once at boot time. Without this patch, programs will get random memory corruption (segmentation fault, bus error, etc.) while CPU Hotplug (e.g. one CPU is using clear_page() while another is generating it in cpu_cache_init()). For similar reasons we modify build_tlb_refill_handler()'s invocation. V2: 1, Rework the code to make CPU#0 can be online/offline. 2, Introduce cpu_has_local_ebase feature since some types of MIPS CPU need a per-CPU tlb_refill_handler(). Signed-off-by: NHuacai Chen <chenhc@lemote.com> Signed-off-by: NHongbing Hu <huhb@lemote.com> Acked-by: NDavid Daney <david.daney@cavium.com> Patchwork: http://patchwork.linux-mips.org/patch/4994/Acked-by: NJohn Crispin <blogic@openwrt.org>
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- 02 5月, 2013 3 次提交
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由 Steven J. Hill 提交于
Some MIPS controllers have hardware I/O coherency. This patch detects those and turns off software coherency. A new kernel command line option also allows the user to manually turn software coherency on or off. Signed-off-by: NSteven J. Hill <Steven.Hill@imgtec.com>
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由 Steven J. Hill 提交于
Add new file 'uasm-micromips.c' that allows the micro assembler to generate microMIPS ISA code. It can be included in the kernel alongside the classic ISA as long as the platform supports the microMIPS ISA. Signed-off-by: NSteven J. Hill <sjhill@mips.com> Cc: linux-mips@linux-mips.org Cc: cernekee@gmail.com Cc: kevink@paralogos.com Cc: ddaney.cavm@gmail.com Patchwork: https://patchwork.linux-mips.org/patch/4923/Signed-off-by: NRalf Baechle <ralf@linux-mips.org> (cherry picked from commit 5f011a866afbd03a5379f67f4e70e5efbdfc16e9)
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由 Steven J. Hill 提交于
Split 'uasm.c' into two files. The new file 'uasm-mips.c' has the functions specific to the classic MIPS ISA. The 'uasm.c' file contains common code that can be used by classic or other ISAs that could be supported by the kernel. Signed-off-by: NSteven J. Hill <sjhill@mips.com> Cc: linux-mips@linux-mips.org Cc: cernekee@gmail.com Cc: kevink@paralogos.com Cc: ddaney.cavm@gmail.com Patchwork: https://patchwork.linux-mips.org/patch/4922/Signed-off-by: NRalf Baechle <ralf@linux-mips.org> (cherry picked from commit 0961103562ab958fa74f35043bf4f72e51ed6155)
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- 30 4月, 2013 3 次提交
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由 Jiang Liu 提交于
Use helper function free_highmem_page() to free highmem pages into the buddy system. Signed-off-by: NJiang Liu <jiang.liu@huawei.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: David Daney <david.daney@cavium.com> Cc: Cong Wang <amwang@redhat.com> Cc: Arnd Bergmann <arnd@arndb.de> Signed-off-by: NAndrew Morton <akpm@linux-foundation.org> Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
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由 Jiang Liu 提交于
Use common help functions to free reserved pages. Signed-off-by: NJiang Liu <jiang.liu@huawei.com> Cc: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: NAndrew Morton <akpm@linux-foundation.org> Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
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由 David Howells 提交于
Split kcore bits from linux/procfs.h into linux/kcore.h. Signed-off-by: NDavid Howells <dhowells@redhat.com> Acked-by: NKOSAKI Motohiro <kosaki.motohiro@jp.fujitsu.com> Acked-by: NRalf Baechle <ralf@linux-mips.org> cc: linux-mips@linux-mips.org cc: sparclinux@vger.kernel.org cc: x86@kernel.org cc: linux-mm@kvack.org Signed-off-by: NAl Viro <viro@zeniv.linux.org.uk>
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- 11 4月, 2013 1 次提交
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由 Ralf Baechle 提交于
tlbmiss_handler_setup_pgd is run-time generated code and it was convenient to pretend the symbol was an array in the generator but a function for the users. LTO gcc won't tolerate this kind of lie anymore so solve the problem through a cast and function pointer instead. Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 05 4月, 2013 1 次提交
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由 Deng-Cheng Zhu 提交于
The commit a96102be introduced set_isa() where compatible ISA info is also set aside from the one gets passed in. It means, for example, 1004K will have MIPS_CPU_ISA_M32R2/M32R1/II/I flags. This leads to things like the following inappropriate: if (c->isa_level == MIPS_CPU_ISA_M32R1 || c->isa_level == MIPS_CPU_ISA_M32R2 || c->isa_level == MIPS_CPU_ISA_M64R1 || c->isa_level == MIPS_CPU_ISA_M64R2) This patch fixes it. Signed-off-by: NDeng-Cheng Zhu <dengcheng.zhu@imgtec.com> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: linux-mips@linux-mips.org Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 17 2月, 2013 1 次提交
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由 Steven J. Hill 提交于
Signed-off-by: NSteven J. Hill <sjhill@mips.com> Patchwork: http://patchwork.linux-mips.org/patch/4682/Signed-off-by: NJohn Crispin <blogic@openwrt.org>
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- 01 2月, 2013 1 次提交
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由 Ralf Baechle 提交于
Having received another series of whitespace patches I decided to do this once and for all rather than dealing with this kind of patches trickling in forever. Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 31 1月, 2013 1 次提交
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由 Steven Rostedt 提交于
Commit d3ce8843 "MIPS: Fix modpost error in modules attepting to use virt_addr_valid()" moved __virt_addr_valid() from a macro in a header file to a function in ioremap.c. But ioremap.c is only compiled for MIPS 32, and not for MIPS 64. When compiling for my yeeloong2, which supposedly supports hibernation, which compiles kernel/power/snapshot.c which calls virt_addr_valid(), I got this error: LD init/built-in.o kernel/built-in.o: In function `memory_bm_free': snapshot.c:(.text+0x4c9c4): undefined reference to `__virt_addr_valid' snapshot.c:(.text+0x4ca58): undefined reference to `__virt_addr_valid' kernel/built-in.o: In function `snapshot_write_next': (.text+0x4e44c): undefined reference to `__virt_addr_valid' kernel/built-in.o: In function `snapshot_write_next': (.text+0x4e890): undefined reference to `__virt_addr_valid' make[1]: *** [vmlinux] Error 1 make: *** [sub-make] Error 2 I suspect that __virt_addr_valid() is fine for mips 64. I moved it to mmap.c such that it gets compiled for mips 64 and 32. Signed-off-by: NSteven Rostedt <rostedt@goodmis.org> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/4842/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 29 12月, 2012 2 次提交
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由 Ralf Baechle 提交于
ERROR: "min_low_pfn" [drivers/block/aoe/aoe.ko] undefined! Fixed by moving the implementation of virt_addr_valid() into the kernel proper and exporting it which removes the pains of an inline or macro implementation. Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Ralf Baechle 提交于
So far we're jumping through hoops to keep the file usable from assembler source but it's getting just too painful. Turns out that many uses of <asm/page.h> are unnecessary anyway, so just remove those. Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 27 12月, 2012 1 次提交
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由 Ralf Baechle 提交于
This reverts commit ff401e52. This breaks on MIPS64 R2 cores such as Broadcom's.
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- 14 12月, 2012 4 次提交
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由 Ralf Baechle 提交于
Nobody seems to be interested anymore and upstream also never had an ethernet driver. Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Ralf Baechle 提交于
CC arch/mips/mm/highmem.o /home/ralf/src/linux/linux-mips/arch/mips/mm/highmem.c: In function ‘__kunmap_atomic’: /home/ralf/src/linux/linux-mips/arch/mips/mm/highmem.c:70:6: error: variable ‘type’ set but not used [-Werror=unused-but-set-variable] cc1: all warnings being treated as errors This warning exists in gcc 4.6.0 and newer. Kernels 2.6.40 and newer use -Wunused-but-set-variable to suppress it. Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Ralf Baechle 提交于
Normally r4k_dma_cache_inv should only ever be called with cacheline aligned addresses. If however, it isn't there is the theoretical possibility of data corruption. There is no correct way of handling this and anyway, it should only happen if the DMA API is used incorrectly so drop There is a different corruption scenario with these CACHE instructions removed but again there is no way of handling this correctly and it can be triggered only through incorrect use of the DMA API. So just get rid of the complexity. Signed-off-by: NRalf Baechle <ralf@linux-mips.org> Reported-by: NJames Rodriguez <jamesr@juniper.net>
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由 David Daney 提交于
Some initialization errors are reported with the existing OCTEON EDAC support patch. Also some parts have more than one memory controller. Fix the errors and add multiple controllers if present. Signed-off-by: NDavid Daney <david.daney@cavium.com>
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- 12 12月, 2012 4 次提交
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由 Ralf Baechle 提交于
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Ralf Baechle 提交于
Drivers for EDAC on Cavium. Supported subsystems are: o CPU primary caches. These are parity protected only, so only error reporting. o Second level cache - ECC protected, provides SECDED. o Memory: ECC / SECDEC if used with suitable DRAM modules. The driver will will only initialize if ECC is enabled on a system so is safe to run on non-ECC memory. o PCI: Parity error reporting Since it is very hard to test this sort of code the implementation is very conservative and uses polling where possible for now. Signed-off-by: NRalf Baechle <ralf@linux-mips.org> Reviewed-by: NBorislav Petkov <borislav.petkov@amd.com>
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由 David Daney 提交于
We need Huge TLBs for HUGETLB_PAGE, or the soon to follow TRANSPARENT_HUGEPAGE. collect this information under a single Kconfig symbol. Signed-off-by: NDavid Daney <david.daney@cavium.com>
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由 Michel Lespinasse 提交于
Update the mips arch_get_unmapped_area[_topdown] functions to make use of vm_unmapped_area() instead of implementing a brute force search. [akpm@linux-foundation.org: remove now-unused COLOUR_ALIGN_DOWN()] Signed-off-by: NMichel Lespinasse <walken@google.com> Reviewed-by: NRik van Riel <riel@redhat.com> Cc: Hugh Dickins <hughd@google.com> Cc: Russell King <linux@arm.linux.org.uk> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Paul Mundt <lethal@linux-sh.org> Cc: "David S. Miller" <davem@davemloft.net> Cc: Chris Metcalf <cmetcalf@tilera.com> Cc: Ingo Molnar <mingo@elte.hu> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: "H. Peter Anvin" <hpa@zytor.com> Signed-off-by: NAndrew Morton <akpm@linux-foundation.org> Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
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- 04 12月, 2012 1 次提交
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由 David Daney 提交于
Problem: 1) Huge page mapping of anonymous memory is initially invalid. Will be faulted in by copy-on-write mechanism. 2) Userspace attempts store at the end of the huge mapping. 3) TLB Refill exception handler fill TLB with a normal (4K sized) invalid page at the end of the huge mapping virtual address range. 4) Userspace restarted, and re-attempts the store at the end of the huge mapping. 5) Page from #3 is invalid, we get a fault and go to the hugepage fault handler. This tries to map a huge page and calls huge_ptep_set_access_flags() to install the mapping. 6) We just call the generic ptep_set_access_flags() to set up the page tables, but the flush there assumes a normal (4K sized) page and only tries to flush the first part of the huge page virtual address out of the TLB, since the existing entry from step #3 doesn't conflict, nothing is flushed. 7) We attempt to load the mapping into the TLB, but because it conflicts with the entry from step #3, we get a Machine Check exception. The fix: Flush the entire rage covered by the huge page in huge_ptep_set_access_flags(), and remove the optimization in local_flush_tlb_range() so that the flush actually does the correct thing. Signed-off-by: NDavid Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: Hillf Danton <dhillf@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/4661/Signed-off-by: NRalf Baechle <ralf@linux-mips.org> (cherry picked from commit dd617f258cc39d36be26afee9912624a2d23112c)
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- 26 11月, 2012 2 次提交
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由 Ralf Baechle 提交于
Pgtable bits are assigned dynamically depending on processor feature and statically based on kernel configuration. To make sense out of the disassembled TLB exception handlers a list of the actual assignments used for a particular configuration and hardware setup can be very useful. Output the actual TLB exception handlers in a format that simplifies their post processsing from dmesg output. Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Ralf Baechle 提交于
From a software perspective R5000 and R5000A are the same thing which is why the symbol CPU_R5000A never got used, so finally delete it. Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 09 11月, 2012 2 次提交
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由 Shane McDonald 提交于
Commit 97ce2c88 (jump-label: initialize jump-label subsystem much earlier) caused MIPS to break, so this was resolved with commit 6650df3c (MIPS: Move cache setup to setup_arch().). Unfortunately, after this commit, the coherency kernel parameters, cca and coherentio, are no longer processed before their values are used. This patch fixes this problem by marking them as early_param, which results in them being processed before they are needed. Signed-off-by: NShane McDonald <mcdonald.shane@gmail.com> Acked-by: NDavid Daney <david.daney@cavium.com> Cc: Ralf Baechle <ralf@linux-mips.org> Patchwork: http://patchwork.linux-mips.org/patch/3961Signed-off-by: NJohn Crispin <blogic@openwrt.org>
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由 Kevin Cernekee 提交于
The new functions introduced in commit 02a54177 (MIPS: tlbex: Deal with re-definition of label) should be marked __cpuinit, to eliminate a warning that can pop up when CONFIG_EXPORT_UASM is disabled: LD arch/mips/mm/built-in.o WARNING: arch/mips/mm/built-in.o(.text+0x2a4c): Section mismatch in reference from the function uasm_bgezl_hazard() to the function .cpuinit.text:uasm_il_bgezl() The function uasm_bgezl_hazard() references the function __cpuinit uasm_il_bgezl(). This is often because uasm_bgezl_hazard lacks a __cpuinit annotation or the annotation of uasm_il_bgezl is wrong. WARNING: arch/mips/mm/built-in.o(.text+0x2a68): Section mismatch in reference from the function uasm_bgezl_label() to the function .cpuinit.text:uasm_build_label() The function uasm_bgezl_label() references the function __cpuinit uasm_build_label(). This is often because uasm_bgezl_label lacks a __cpuinit annotation or the annotation of uasm_build_label is wrong. (This warning might not occur if the function was inlined.) Signed-off-by: NKevin Cernekee <cernekee@gmail.com> Patchwork: http://patchwork.linux-mips.org/patch/4517Signed-off-by: NJohn Crispin <blogic@openwrt.org>
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- 17 10月, 2012 2 次提交
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由 Ralf Baechle 提交于
On some CPU the write to pagemask might complete before the TLB write instruction reads from the pagemask register. Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Ralf Baechle 提交于
R5000 and the Nevada CPUs (RM5230, RM5231, RM5260, RM5261, RM5270 and RM5271) are basically the same CPU core and all are documented to require two instructions separating a write to c0_pagemask, c0_entryhi, c0_entrylo0, c0_entrylo1 or c0_index. So far we were only providing on cycle before / after a TLBR/TLBWI for R5000 but 3 cycles before and 1 cycles after for the Nevadas. Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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