- 14 5月, 2012 1 次提交
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由 Axel Lin 提交于
Signed-off-by: NAxel Lin <axel.lin@gmail.com> Cc: Eric Miao <eric.y.miao@gmail.com> Tested-by: NPaul Parsons <lost.distance@yahoo.com> Acked-by: NPhilipp Zabel <philipp.zabel@gmail.com> Acked-by: NRobert Jarzmik <robert.jarzmik@free.fr> Acked-by: NMarek Vasut <marek.vasut@gmail.com> Acked-by: NJonathan Cameron <jic23@cam.ac.uk> Signed-off-by: NHaojian Zhuang <haojian.zhuang@gmail.com>
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- 13 5月, 2012 7 次提交
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由 Kukjin Kim 提交于
It should be (1 << 2) for ctrlbit of exynos5_clk_pdma1. Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
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由 Marek Szyprowski 提交于
Commit 069d4e74 ("ARM: EXYNOS4: Remove clock event timers using ARM private timers") removed support for local timers and forced to use MCT as event source. However MCT is not operating properly on early revision of EXYNOS4 SoCs. All UniversalC210 boards are based on it, so that commit broke support for it. This patch provides a workaround that enables UniversalC210 boards to boot again. s5p-timer is used as an event source, it works only for non-SMP builds. Signed-off-by: NMarek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
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由 Magnus Damm 提交于
Make sure L1 caches are invalidated when booting secondary cores. Needed to boot all mach-shmobile SMP systems that are using Cortex-A9 including sh73a0, r8a7779 and EMEV2. Thanks to imx and tegra guys for actual code. Signed-off-by: NMagnus Damm <damm@opensource.se> Tested-by: NKuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: NRafael J. Wysocki <rjw@sisk.pl>
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由 Kuninori Morimoto 提交于
Fix SMP TWD boot regression on sh73a0 based platforms caused by: 4200b16d ARM: shmobile: convert to twd_local_timer_register() interface After the merge of the above commit it has been impossible to boot sh73a0 based SoCs with SMP enabled and CONFIG_HAVE_ARM_TWD=y. The kernel crashes at smp_init_cpus() timing which is before the console has been initialized, so to the user this looks like a kernel lock up without any particular error message. This patch fixes the regression on sh73a0 by moving the TWD registration code from smp_init_cpus() to sys_timer->init() time. This patch removed shmobile_twd_init() which is no longer needed Signed-off-by: NKuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: NMagnus Damm <damm@opensource.se> Signed-off-by: NRafael J. Wysocki <rjw@sisk.pl>
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由 Magnus Damm 提交于
Fix SMP TWD boot regression on r8a7779 based platforms caused by: 4200b16d ARM: shmobile: convert to twd_local_timer_register() interface After the merge of the above commit it has been impossible to boot r8a7779 based SoCs with SMP enabled and CONFIG_HAVE_ARM_TWD=y. The kernel crashes at smp_init_cpus() timing which is before the console has been initialized, so to the user this looks like a kernel lock up without any particular error message. This patch fixes the regression on r8a7779 by moving the TWD registration code from smp_init_cpus() to sys_timer->init() time. Signed-off-by: NMagnus Damm <damm@opensource.se> Acked-by: NMarc Zyngier <marc.zyngier@arm.com> Signed-off-by: NRafael J. Wysocki <rjw@sisk.pl>
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由 Guennadi Liakhovetski 提交于
This also fixes the following modular mmc build failure: arch/arm/mach-shmobile/built-in.o: In function `mackerel_sdhi0_gpio_cd': pfc-sh7372.c:(.text+0x1138): undefined reference to `mmc_detect_change' on this platform by eliminating the use of an inline function, which calls into the mmc core. Signed-off-by: NGuennadi Liakhovetski <g.liakhovetski@gmx.de> Reviewed-by: NSimon Horman <horms@verge.net.au> Acked-by: NMagnus Damm <damm@opensource.se> Signed-off-by: NRafael J. Wysocki <rjw@sisk.pl>
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由 Guennadi Liakhovetski 提交于
This also fixes the following modular mmc build failure: arch/arm/mach-shmobile/built-in.o: In function `ag5evm_sdhi0_gpio_cd': pfc-sh73a0.c:(.text+0x7c0): undefined reference to `mmc_detect_change' on this platform by eliminating the use of an inline function, which calls into the mmc core. Signed-off-by: NGuennadi Liakhovetski <g.liakhovetski@gmx.de> Tested-by: NSimon Horman <horms@verge.net.au> Acked-by: NMagnus Damm <damm@opensource.se> Signed-off-by: NRafael J. Wysocki <rjw@sisk.pl>
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- 09 5月, 2012 3 次提交
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由 Enrico Butera 提交于
id 0 is already used and causes errors at boot: WARNING: at fs/sysfs/dir.c:508 sysfs_add_one+0x9c/0xac() sysfs: cannot create duplicate filename '/devices/platform/reg-fixed-voltage.0' Fix it by using the next available one (id=1). This was caused by 5b3689f4 (ARM: OMAP2+: smsc911x: Add fixed board regulators) that did not account for some regulators already being used. Signed-off-by: NEnrico Butera <ebutera@users.berlios.de> [tony@atomide.com: updated comments for regression causing commit] Signed-off-by: NTony Lindgren <tony@atomide.com>
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由 Ben Hutchings 提交于
Commit 554cdaef ('ARM: orion5x: Refactor mpp code to use common orion platform mpp.') seems to have accidentally inverted the GPIO valid bits for MPP9 (only). For the mv2120 platform which uses MPP9 as a GPIO LED device, this results in the error: [ 12.711476] leds-gpio: probe of leds-gpio failed with error -22 Reported-by: NHenry von Tresckow <hvontres@gmail.com> References: http://bugs.debian.org/667446Signed-off-by: NBen Hutchings <ben@decadent.org.uk> Cc: stable@vger.kernel.org [v3.0+] Tested-by: NHans Henry von Tresckow <hvontres@gmail.com> Signed-off-by: NJason Cooper <jason@lakedaemon.net>
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由 Ian Campbell 提交于
Fixes the following build error when CONFIG_KEXEC is enabled: CC arch/arm/mach-kirkwood/board-dt.o arch/arm/mach-kirkwood/board-dt.c: In function 'kirkwood_dt_init': arch/arm/mach-kirkwood/board-dt.c:52:2: error: 'kexec_reinit' undeclared (first use in this function) arch/arm/mach-kirkwood/board-dt.c:52:2: note: each undeclared identifier is reported only once for each function it appears in Signed-off-by: NIan Campbell <ijc@hellion.org.uk> [v4, rebase onto recent Linus for repost] [v3, speak actual English in the commit message, thanks Sergei Shtylyov] [v2, using linux/kexec.h not asm/kexec.h] Signed-off-by: NJason Cooper <jason@lakedaemon.net>
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- 06 5月, 2012 1 次提交
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由 Colin Cross 提交于
Commit 4e8ee7de (ARM: SMP: use idmap_pgd for mapping MMU enable during secondary booting) switched secondary boot to use idmap_pgd, which is initialized during early_initcall, instead of a page table initialized during __cpu_up. This causes idmap_pgd to contain the static mappings but be missing all dynamic mappings. If a console is registered that creates a dynamic mapping, the printk in secondary_start_kernel will trigger a data abort on the missing mapping before the exception handlers have been initialized, leading to a hang. Initial boot is not affected because no consoles have been registered, and resume is usually not affected because the offending console is suspended. Onlining a cpu with hotplug triggers the problem. A workaround is to the printk in secondary_start_kernel until after the page tables have been switched back to init_mm. Cc: <stable@vger.kernel.org> Signed-off-by: NColin Cross <ccross@android.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 05 5月, 2012 5 次提交
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由 Will Deacon 提交于
The machine endianness has no direct correspondence to the syscall ABI, so use only AUDIT_ARCH_ARM when identifying the ABI to the audit tools in userspace. Cc: stable@vger.kernel.org Signed-off-by: NWill Deacon <will.deacon@arm.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Will Deacon 提交于
The ARM audit code incorrectly uses the saved application ip register value to infer syscall entry or exit. Additionally, the saved value will be clobbered if the current task is not being traced, which can lead to libc corruption if ip is live (apparently glibc uses it for the TLS pointer). This patch fixes the syscall tracing code so that the why parameter is used to infer the syscall direction and the saved ip is only updated if we know that we will be signalling a ptrace trap. Reported-and-Tested-by: NJon Masters <jcm@jonmasters.org> Cc: stable@vger.kernel.org Cc: Eric Paris <eparis@redhat.com> Signed-off-by: NWill Deacon <will.deacon@arm.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Tim Bird 提交于
The inline assembly in kernel_execve() uses r8 and r9. Since this code sequence does not return, it usually doesn't matter if the register clobber list is accurate. However, I saw a case where a particular version of gcc used r8 as an intermediate for the value eventually passed to r9. Because r8 is used in the inline assembly, and not mentioned in the clobber list, r9 was set to an incorrect value. This resulted in a kernel panic on execution of the first user-space program in the system. r9 is used in ret_to_user as the thread_info pointer, and if it's wrong, bad things happen. Cc: <stable@vger.kernel.org> Signed-off-by: NTim Bird <tim.bird@am.sony.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Archit Taneja 提交于
This reverts commit 46f8c3c7. The commit above swapped the DSI1_PPID and DSI2_PPID register fields in CONTROL_DSIPHY to be in sync with the newer public OMAP TRMs(after version V). With this commit, contention errors were reported on DSI lanes some OMAP4 SDPs. After probing the DSI lanes on OMAP4 SDP, it was seen that setting bits in the DSI2_PPID field was pulling up voltage on DSI1 lanes, and DSI1_PPID field was pulling up voltage on DSI2 lanes. This proves that the current version of OMAP4 TRM is incorrect, swap the position of register fields according to the older TRM versions as they were correct. Cc: stable@vger.kernel.org # v3.2+ Acked-by: NTomi Valkeinen <tomi.valkeinen@ti.com> Signed-off-by: NArchit Taneja <archit@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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由 Janusz Krzysztofik 提交于
Commit 384ebe1c, "gpio/omap: Add DT support to GPIO driver", introduced dynamic IRQ numbering of OMAP GPIO interrupts, breaking all IH_GPIO_BASE based IRQ number calculations. This issue was corrected in the OMAP GPIO driver and the related header file with commit 25db711d, "gpio/omap: Fix IRQ handling for SPARSE_IRQ". However, the Amstrad Delta FIQ handler, which replaces the gpio-omap driver in serving GPIO interrupts on this board, still uses that outdated method. Fix it. Signed-off-by: NJanusz Krzysztofik <jkrzyszt@tis.icnet.pl> Signed-off-by: NTony Lindgren <tony@atomide.com>
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- 28 4月, 2012 4 次提交
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由 Will Deacon 提交于
When a CPU is hotplugged off, we migrate any IRQs currently affine to it away and onto another online CPU by calling the irq_set_affinity function of the relevant interrupt controller chip. This function returns either IRQ_SET_MASK_OK or IRQ_SET_MASK_OK_NOCOPY, to indicate whether irq_data.affinity was updated. If we are forcefully migrating an interrupt (because the affinity mask no longer identifies any online CPUs) then we should update the IRQ affinity mask to reflect the new CPU set. Failure to do so can potentially leave /proc/irq/n/smp_affinity identifying only offline CPUs, which may confuse userspace IRQ balancing daemons. This patch updates migrate_one_irq to copy the affinity mask when the interrupt chip returns IRQ_SET_MASK_OK after forcefully changing the affinity of an interrupt. Cc: stable@vger.kernel.org Reported-by: NLeif Lindholm <leif.lindholm@arm.com> Signed-off-by: NWill Deacon <will.deacon@arm.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Will Deacon 提交于
When performing a kexec on an SMP system, the secondary cores are stopped by calling machine_shutdown(), which in turn issues IPIs to offline the other CPUs. Unfortunately, this isn't enough to reboot the cores into a new kernel (since they are just executing a cpu_relax loop somewhere in memory) so we make use of platform_cpu_kill, part of the CPU hotplug implementation, to place the cores somewhere safe. This function expects to be called on the killing CPU for each core that it takes out. This patch moves the platform_cpu_kill callback out of the IPI handler and into smp_send_stop, therefore ensuring that it executes on the killing CPU rather than on the victim, matching what the hotplug code requires. Cc: stable@vger.kernel.org Reported-by: NRussell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: NWill Deacon <will.deacon@arm.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Will Deacon 提交于
TPIDRURW is a user read/write register forming part of the group of thread registers in more recent versions of the ARM architecture (~v6+). Currently, the kernel does not touch this register, which allows tasks to communicate covertly by reading and writing to the register without context-switching affecting its contents. This patch clears TPIDRURW when TPIDRURO is updated via the set_tls macro, which is called directly from __switch_to. Since the current behaviour makes the register useless to userspace as far as thread pointers are concerned, simply clearing the register (rather than saving and restoring it) will not cause any problems to userspace. Cc: stable@vger.kernel.org Signed-off-by: NWill Deacon <will.deacon@arm.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Stephen Boyd 提交于
WARNING: vmlinux.o(.text+0x111b8): Section mismatch in reference from the function arm_memory_present() to the function .init.text:memory_present() The function arm_memory_present() references the function __init memory_present(). This is often because arm_memory_present lacks a __init annotation or the annotation of memory_present is wrong. WARNING: arch/arm/mm/built-in.o(.text+0x1edc): Section mismatch in reference from the function alloc_init_pud() to the function .init.text:alloc_init_section() The function alloc_init_pud() references the function __init alloc_init_section(). This is often because alloc_init_pud lacks a __init annotation or the annotation of alloc_init_section is wrong. Signed-off-by: NStephen Boyd <sboyd@codeaurora.org> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 27 4月, 2012 4 次提交
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由 Igor Grinberg 提交于
Pins configured as input and have MFP_LPM_DRIVE_* flag set, can have a wrong output value for some period of time (spike) during the suspend sequence. This can happen because the direction of the pins (GPDR) is set by software and the output level is set by hardware (PGSR) at a later stage. Fix the above potential bug by setting the output levels first. Also save the actual levels of the pins before the suspend and restore them after the resume, but before the direction settings take place, so the same bug as described above will not happen in the resume sequence. Reported-by: NPaul Parsons <lost.distance@yahoo.com> Signed-off-by: NIgor Grinberg <grinberg@compulab.co.il> Tested-by: NPaul Parsons <lost.distance@yahoo.com> Signed-off-by: NHaojian Zhuang <haojian.zhuang@gmail.com>
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由 Igor Grinberg 提交于
Pins that have MFP_LPM_KEEP_OUTPUT set and are configured for output must retain the output state in low power mode. Currently, the pin direction configuration is overrided with values in gpdr_lpm[] array and do not obey the MFP_LPM_KEEP_OUTPUT setting. Fix the above bug and add some documentation to clarify the MFP_LPM_KEEP_OUTPUT setting purpose. Reported-by: NPaul Parsons <lost.distance@yahoo.com> Signed-off-by: NIgor Grinberg <grinberg@compulab.co.il> Tested-by: NPaul Parsons <lost.distance@yahoo.com> Signed-off-by: NHaojian Zhuang <haojian.zhuang@gmail.com>
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由 Dmitry Artamonow 提交于
DEFINE_RES_MEM() takes the size of resource as a second argument, not the end address. Passing end address leads to following error in runtime during device registration: sa1100-rtc: failed to claim resource 0 Fix it. Signed-off-by: NDmitry Artamonow <mad_soft@inbox.ru> Signed-off-by: NHaojian Zhuang <haojian.zhuang@gmail.com>
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由 Robert Jarzmik 提交于
In 3.3, gpio wakeup setting was broken. The call enable_irq_wake() didn't set up the PXA gpio registers (PWER, ...) anymore. Fix it at least for pxa27x. The driver doesn't seem to be used in pxa25x (weird ...), and the fix doesn't extend to pxa3xx and pxa95x (which don't have a gpio_set_wake() available). Signed-off-by: NRobert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: NHaojian Zhuang <haojian.zhuang@gmail.com>
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- 26 4月, 2012 1 次提交
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由 Vasiliy Kulikov 提交于
Don't allow everybody to use a modem. Signed-off-by: NVasiliy Kulikov <segoon@openwall.com> Cc: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com> Acked-by: NLinus Walleij <linus.walleij@linaro.org> Cc: Russell King <linux@arm.linux.org.uk> Signed-off-by: NAndrew Morton <akpm@linux-foundation.org> Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
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- 25 4月, 2012 5 次提交
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由 Marek Szyprowski 提交于
Commit 6e8201f5 "mmc: core: add the capability for broken voltage" introduced a new quirk to indicate that MMC core should ignore voltage change errors reported by the regulators core. This is required to get SDHCI working on UniversalC210, NURI and GONI boards again after commit ceb6143b ("mmc: sdhci: fix vmmc handling"). Signed-off-by: NMarek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
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由 Tushar Behera 提交于
Fixed following compile time error. arch/arm/mach-exynos/common.c: In function 'exynos5_init_irq': arch/arm/mach-exynos/common.c:539:2: error: implicit declaration of function 'of_irq_init' arch/arm/mach-exynos/common.c:539:14: error: 'exynos4_dt_irq_match' undeclared (first use in this function) arch/arm/mach-exynos/common.c:539:14: note: each undeclared identifier is reported only once for each function it appears in Cc: Thomas Abraham <thomas.abraham@linaro.org> Signed-off-by: NTushar Behera <tushar.behera@linaro.org> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
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由 Kukjin Kim 提交于
Should be EXYNOS4_IRQ_DWMCI instead of IRQ_DWMCI, and use DEFINE_RES_{MEM,IRQ}. Reported-by: NJaehoon Chung <jh80.chung@samsung.com> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
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由 Kukjin Kim 提交于
warning: (CPU_S3C2440 && CPU_S3C2442) selects S3C2410_PM which has unmet direct dependencies (ARCH_S3C24XX && CPU_S3C2410) warning: (CPU_S3C2440 && CPU_S3C2442) selects S3C2410_PM which has unmet direct dependencies (ARCH_S3C24XX && CPU_S3C2410) Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
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由 Arnd Bergmann 提交于
This is needed to fix mini2440_defconfig after the platform files have been moved around. arm-none-linux-gnueabi-ld: no machine record defined arm-none-linux-gnueabi-ld: no machine record defined arm-none-linux-gnueabi-ld: no machine record defined make: *** [.tmp_vmlinux1] Error 1 Signed-off-by: NArnd Bergmann <arnd@arndb.de> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
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- 24 4月, 2012 1 次提交
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由 David Brown 提交于
As of commit 75294957 Author: Grant Likely <grant.likely@secretlab.ca> Date: Tue Feb 14 14:06:57 2012 -0700 irq_domain: Remove 'new' irq_domain in favour of the ppc one the ARM gic controller uses proper irq domains. Fix the MSM gic initialization and DT so that it works again. Signed-off-by: NDavid Brown <davidb@codeaurora.org> Acked-by: NGrant Likely <grant.likely@secretlab.ca>
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- 23 4月, 2012 7 次提交
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由 Russell King 提交于
Using coherent DMA memory with the OMAP DMA engine results in unpredictable behaviour due to memory ordering issues; as things stand, there is no guarantee that data written to coherent DMA memory will be visible to the DMA hardware. This is because the OMAP dma_write() accessor contains no barriers, necessary on ARMv6 and above. The effect of this can be seen in comments in the OMAP serial driver, which incorrectly talks about cache flushing for the coherent DMA stuff. Rather than adding barriers to the accessors, add it in the DMA support code just before we enable DMA, and just after we disable DMA. This avoids having barriers for every DMA register access. Acked-by: NTony Lindgren <tony@atomide.com> Acked-by: NSantosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Linus Walleij 提交于
The MMCI driver will not work without two IRQs since this is not flagged as a single-irq variant. Looking through the complex IRQ definition for the MMCI on the versatile (including an #if 1 statement forcing MMCI IRQ0 to the VIC) this appears to the the correct IRQ number for both models. Cc: Niklas Hernaeus <niklas.hernaeus@linaro.org> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Will Deacon 提交于
The ARM PCS mandates that the length and stride bits of the fpscr are cleared on entry to and return from a public interface. Although signal handlers run asynchronously with respect to the interrupted function, the handler itself expects to run as though it has been called like a normal function. This patch updates the state mirroring the VFP hardware before entry to a signal handler so that it adheres to the PCS. Furthermore, we disable VFP to ensure that we trap on any floating point operation performed by the signal handler and synchronise the hardware appropriately. A check is inserted after the signal handler to avoid redundant flushing if VFP was not used. Reported-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NWill Deacon <will.deacon@arm.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Will Deacon 提交于
The user VFP state must be preserved (subject to ucontext modifications) across invocation of a signal handler and this is currently handled by vfp_{preserve,restore}_context in signal.c Since this code requires intimate low-level knowledge of the VFP state, this patch moves it into vfpmodule.c. Signed-off-by: NWill Deacon <will.deacon@arm.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Will Deacon 提交于
PL310 errata #588369 and #727915 require writes to the debug registers of the cache controller to work around known problems. Writing these registers on L220 may cause deadlock, so ensure that we only perform this operation when we identify a PL310 at probe time. Cc: stable@vger.kernel.org Signed-off-by: NWill Deacon <will.deacon@arm.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Will Deacon 提交于
The workaround for PL310 erratum #753970 can lead to deadlock on systems with an L220 cache controller. This patch makes the workaround effective only when the cache controller is identified as a PL310 at probe time. Cc: stable@vger.kernel.org Signed-off-by: NWill Deacon <will.deacon@arm.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Will Deacon 提交于
Erratum #326103 ("FSR write bit incorrect on a SWP to read-only memory") only affects the ARM 1136 core prior to r1p0. The workaround disassembles the faulting instruction to determine whether it was a read or write access on all v6 cores. An issue has been reported on the ARM 11MPCore whereby loading the faulting instruction may happen in parallel with that page being unmapped, resulting in a deadlock due to the lack of TLB broadcasting in hardware: http://lists.infradead.org/pipermail/linux-arm-kernel/2012-March/091561.html This patch limits the workaround so that it is only used on affected cores, which are known to be UP only. Other v6 cores can rely on the FSR to indicate the access type correctly. Cc: stable@vger.kernel.org Signed-off-by: NWill Deacon <will.deacon@arm.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 21 4月, 2012 1 次提交
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由 Thomas Abraham 提交于
Use the of_irq_init() call to setup the gic which also properly registers the gic device node pointer with gic irq domain, without which all interrupt specifier translations for gic fail. Signed-off-by: NThomas Abraham <thomas.ab@samsung.com> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
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