Add cached device type for ioremap_cached().  Group all device memory
types together, and ensure that they all have a "MT_DEVICE" prefix.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Change the memory types table to define the L1 descriptor bit 4 to
be in terms of the ARMv6 definition - execute never.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Add prot_pte_ext to the mem_types table to allow the extended pte
attributes to be passed to set_pte_ext(), thereby permitting us to
specify memory type information for the hardware PTE entries.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

We really want to be using the memory type table in ioremap, so we
only have to do the CPU type fixups in one place.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Rather than our three separate loops to setup mappings (by page
mappings up to a section boundary, then section mappings, and the
remainder by page mappings) convert this to a more conventional
Linux style of a loop over each page table level.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Catalin Marinas at ARM Ltd says:
> The CPU architects in ARM intended supersections only as a way to map
> addresses >= 4GB. Supersections are not mandated by the architecture
> and there is no easy way to detect their hardware support at run-time
> (other than checking for a specific core). From the analysis done in
> ARM, there wasn't a clear performance gain by using supersections
> rather than sections (no significant improvement in the TLB misses).

Therefore, we should avoid using supersections unless there's a real
need (iow, we're mapping addresses >= 4GB).

This means that we can simplify create_mapping() a bit since we will
only use supersection mappings for addresses >= 4GB, which means that
the physical, virtual and length must be multiples of the supersection
mapping size.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

There's now no need to carry around each protection separately.
Instead, pass around the pointer to the entry in the mem_types
array which we're interested in.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Rather than combining the domain for a particular memory type with
the protection information each time we want to use it, do so when
we fix up the mem_type array at initialisation time.

Rename struct mem_types to be mem_type - each structure is one
memory type description, not several.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Lots of places in arch/arm were needlessly including linux/ptrace.h,
resumably because we used to pass a struct pt_regs to interrupt
handlers.  Now that we don't, all these ptrace.h includes are
redundant.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Signed-off-by: NUwe Kleine-König <ukleinek@informatik.uni-freiburg.de>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Replace the very few remaining "depends" Kconfig directives with
"depends on".
Signed-off-by: NRobert P. J. Day <rpjday@mindspring.com>
Signed-off-by: NAdrian Bunk <bunk@stusta.de>

Commit 1c9d3df5 added function prototype
__flush_dcache_page() in include/asm-arm/cacheflush.h.  So we can remove
the prototype for same in arch/arm/mm/fault-armv.c since it is now
redundant to have it there.
Signed-off-by: NGeorge G. Davis <gdavis@mvista.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

The kernel originally supported revB only. This patch enables revC by
default and adds a config option for building the kernel for the revB
platform. Since the SCU base address was hard-coded in the proc-v6.S
file (and only valid for RealView/EB revB), this patch also adds a
more generic support for defining the SCU information.
Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

The PAGE_* user page protection macros don't take into account the
configured memory policy and other architecture specific bits like
the global/ASID and shared mapping bits. Instead of constants let
these depend on a variable fixed up at init just like PAGE_KERNEL.
Signed-off-by: NImre Deak <imre.deak@solidboot.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

This patch adds the support for the L210/L220 (outer) cache
controller. The cache range operations are done by index/way since L2
cache controller only accepts physical addresses.
Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Other platforms other than SMP may have an outer cache.  For these, we
also need to mark the page table walks outer cacheable.  Since marking
the walks always outer cacheable apparantly has no side effects, we
might as well always mark them so.

However, we continue to only mark PTWs shared if we have SMP enabled.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

In consistent_sync(), start + size can end up pointing one byte
beyond the end of the direct RAM mapping.  We shouldn't BUG() when
this happens.
Signed-off-by: NLennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Add support for the Atmel AT91SAM9263 processor.  It is similar to the
AT91SAM9260 but with more integrated peripherals, 5 GPIO banks, etc.

Original patch from Nicolas Ferre.
Signed-off-by: NAndrew Victor <andrew@sanpeople.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

The DMA cache handling functions take virtual addresses, but in the
form of unsigned long arguments.  This leads to a little confusion
about what exactly they take.  So, convert them to take const void *
instead.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

The outer cache can be L2 as on RealView/EB MPCore platform or even L3
or further on ARMv7 cores. This patch adds the generic support for
flushing the outer cache in the DMA operations.
Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

The architecture specification states that TLB operations are
guaranteed to be complete only after the execution of a DSB (Data
Synchronisation Barrier, former Data Write Barrier or Drain Write
Buffer). The branch target cache invalidation is also needed. The ISB
(Instruction Synchronisation Barrier, formerly Prefetch Flush) is
needed unless there will be a return from exception before the
corresponding mapping is used (i.e. user mappings).
Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

On newer architectures (ARMv6, ARMv7), the depth of the prefetch and
branch prediction is implementation defined and there is a small risk
of wrong ASID tagging when changing TTBR0 before setting the new
context id. The recommended solution is to set a reserved ASID during
TTBR changing. This patch reserves ASID 0.
Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

This patch cleans up proc-xsc3:
- Correct a number of typos.
- Fix up indentation in a number of places.
- Change references to the various caches to be more clear about
  whether we're talking about the L1 D, the L1 I or the unified L2
  cache.
- Rename "drain write buffer" to "data write barrier", the official
  name used in the Manzano manual.
- Change the xsc3 cpu name from "XScale-Core3" to "XScale-V3 based
  processor".

Also, since a previously merged patch implements proper support for
using a MAC or iWMMXt coprocessor on xsc3 platforms, we no longer
need to enable access to CP0 on boot.
Signed-off-by: NLennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Supersections do not have a field for the domain and it is always
0. This patch prevents the creation of supersections during ioremap
when DOMAIN_IO is not zero (i.e. !defined(CONFIG_IO_36)).
Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

cosmetic fix so iop333 is not reported as ixp46x
iop333 cpuid = 0x69054210
Signed-off-by: NDan Williams <dan.j.williams@intel.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

show_mem() was assuming incorrectly that the mem_map for any
node started at PFN 0.  This is obviously wrong; fix it to
take account of node_start_pfn.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

fuse does not work on ARM due to cache incoherency issues - fuse wants
to use get_user_pages() to copy data from the current process into
kernel space.  However, since this accesses userspace via the kernel
mapping, the kernel mapping can be out of date wrt data written to
userspace.

This can lead to unpredictable behaviour (in the case of fuse) or data
corruption for direct-IO.

This resolves debian bug #402876
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

If PG_dcache_dirty is set for a page, we need to flush the source page
before performing any copypage operation using a different virtual address.

This fixes the copypage implementations for XScale, StrongARM and ARMv6.

This patch fixes segmentation faults seen in the dynamic linker under
the usage patterns in glibc 2.4/2.5.
Signed-off-by: NRichard Purdie <rpurdie@rpsys.net>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Deepak Saxena has agreed to hand xsc3 maintainership over to me.
Signed-off-by: NLennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Move adjust_cr() into arch/arm/mm/mmu.c, and move irqflags.h to
a more appropriate place in the header file.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

We need to ensure that the area size is page aligned so that
remap_area_pte() doesn't increment the address past the end of
the desired area.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Since we're keeping the ioremap code, we might as well keep it as
close to the standard kernel as possible.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

L_PTE_ASID is not really required to be stored in every PTE, since we
can identify it via the address passed to set_pte_at().  So, create
set_pte_ext() which takes the address of the PTE to set, the Linux
PTE value, and the additional CPU PTE bits which aren't encoded in
the Linux PTE value.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Don't set HWCAP_VFP in the processor support file; not only does it
depend on the processor features, but it also depends on the support
code being present.  Therefore, only set it if the support code
detects that we have a VFP coprocessor attached.

Also, move the VFP handling of the coprocessor access register into
the VFP support code.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

The RX3715 is similar to the H1940 in the way
that suspend to RAM works, so we can use most
of the extant support for the H1940 with only
a few modifictions
Signed-off-by: NBen Dooks <ben-linux@fluff.org>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

The iop348 processor integrates an Xscale (XSC3 512KB L2 Cache) core with a
Serial Attached SCSI (SAS) controller, multi-ported DDR2 memory
controller, 3 Application Direct Memory Access (DMA) controllers, a 133Mhz
PCI-X interface, a x8 PCI-Express interface, and other peripherals to form
a system-on-a-chip RAID subsystem engine.

The iop342 processor replaces the SAS controller with a second Xscale core
for dual core embedded applications.

The iop341 processor is the single core version of iop342.

This patch supports the two Intel customer reference platforms iq81340mc
for external storage and iq81340sc for direct attach (HBA) development.

The developer's manual is available here:
ftp://download.intel.com/design/iio/docs/31503701.pdf

Changelog:
* removed virtual addresses from resource definitions
* cleaned up some unnecessary #include's
Signed-off-by: NDan Williams <dan.j.williams@intel.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

In light of the recent pagefault and filemap_copy_from_user work I've gone
through all the arch pagefault handlers to make sure the inc_preempt_count()
'feature' works as expected.

Several sections of code (including the new filemap_copy_from_user) rely on
the fact that faults do not take locks under increased preempt count.

arch/x86_64 - good
arch/powerpc - good
arch/cris - fixed
arch/i386 - good
arch/parisc - fixed
arch/sh - good
arch/sparc - good
arch/s390 - good
arch/m68k - fixed
arch/ppc - good
arch/alpha - fixed
arch/mips - good
arch/sparc64 - good
arch/ia64 - good
arch/arm - fixed
arch/um - good
arch/avr32 - good
arch/h8300 - NA
arch/m32r - good
arch/v850 - good
arch/frv - fixed
arch/m68knommu - NA
arch/arm26 - fixed
arch/sh64 - fixed
arch/xtensa - good
Signed-off-by: NPeter Zijlstra <a.p.zijlstra@chello.nl>
Acked-by: NNick Piggin <npiggin@suse.de>
Signed-off-by: NAndrew Morton <akpm@osdl.org>
Signed-off-by: NLinus Torvalds <torvalds@osdl.org>

Add support to suspend and resume, using the
H1940's bootloader
Signed-off-by: NBen Dooks <ben-linux@fluff.org>
Signed-off-by: NArnaud Patard <arnaud.patard@rtp-net.org>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>