- 19 8月, 2014 1 次提交
-
-
由 Chen-Yu Tsai 提交于
Add nodes for the 3 i2c controllers found on A23 SoCs to the sun8i DTSI. Signed-off-by: NChen-Yu Tsai <wens@csie.org> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
-
- 17 8月, 2014 9 次提交
-
-
由 Chen-Yu Tsai 提交于
This adds pin-muxing info for the i2c controller / port combinations which are known to be used on actual boards. Signed-off-by: NChen-Yu Tsai <wens@csie.org> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
-
由 Chen-Yu Tsai 提交于
Add nodes for the 3 mmc controllers found on A23 SoCs to the sun8i DTSI. Signed-off-by: NChen-Yu Tsai <wens@csie.org> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
-
由 Chen-Yu Tsai 提交于
This adds pin-muxing info for the mmc controller / port combinations which are known to be used on actual boards. Signed-off-by: NChen-Yu Tsai <wens@csie.org> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
-
由 Chen-Yu Tsai 提交于
The MMC module clocks on sun8i are the same as those found on previous Allwinner SoCs, module 0 clocks. This patch adds the clocks nodes to the dtsi with existing drivers. Signed-off-by: NChen-Yu Tsai <wens@csie.org> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
-
由 Chen-Yu Tsai 提交于
R_UART is available on extra pads on certain tablets, which makes it ideal for use as a console. Here we add the pins for it. Signed-off-by: NChen-Yu Tsai <wens@csie.org> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
-
由 Chen-Yu Tsai 提交于
uart0 on sun8i is only muxed with mmc0, which makes it a poor choice for the console. However, some tablets only have pads for uart0 available on the circuit board. Here we add the uart0 pinmux set for people who need it. Signed-off-by: NChen-Yu Tsai <wens@csie.org> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
-
由 Chen-Yu Tsai 提交于
Now that we have a driver for the R_PIO controller, add the corresponding device node to the dtsi. Signed-off-by: NChen-Yu Tsai <wens@csie.org> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
-
由 Chen-Yu Tsai 提交于
Now that we have a driver for the sun8i PIO controller, add the corresponding device node to the dtsi. Signed-off-by: NChen-Yu Tsai <wens@csie.org> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
-
由 Chen-Yu Tsai 提交于
sun8i shares the same rtc hardware as sun6i. Now that we have a driver for it, add a device node to the DTSI for it so we can use it. Signed-off-by: NChen-Yu Tsai <wens@csie.org> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
-
- 15 7月, 2014 1 次提交
-
-
由 Chen-Yu Tsai 提交于
With sun8i PRCM support available, we can add the PRCM clock and reset controller nodes to the DTSI. Also update R_UART's clock phandle and add it's reset control phandle. Signed-off-by: NChen-Yu Tsai <wens@csie.org> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
-
- 07 7月, 2014 1 次提交
-
-
由 Chen-Yu Tsai 提交于
The A23 has the same MMIO reset controllers matching the clocks gates, just like in the A31. This patch adds the reset controller nodes and the reset control phandles for the peripherals needing them to the DTSI. Unlike the sun6i DTSI, this patch uses sun6i-a31-clock-reset for ahb1_rst. sun6i-a31-ahb-reset is for early init, and requires some additions to the machine code. It is used to support the hstimer. However the hstimer on sun8i only has 1 timer, which is somewhat useless. Support for it will probably not be added. Hence the decision to use sun6i-a31-clock-reset here to avoid the changes to sun8i machine code. Signed-off-by: NChen-Yu Tsai <wens@csie.org> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
-
- 04 7月, 2014 1 次提交
-
-
由 Chen-Yu Tsai 提交于
Now that we have support for sun8i specific clocks in the driver, add the corresponding clock nodes to the DTSI. Also update the existing peripherals with the correct clocks. Signed-off-by: NChen-Yu Tsai <wens@csie.org> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
-
- 01 7月, 2014 1 次提交
-
-
由 Chen-Yu Tsai 提交于
The Allwinner A23 is a tablet oriented SoC with 2 Cortex-A7 cores and a Mali-400MP2 GPU. Signed-off-by: NChen-Yu Tsai <wens@csie.org> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
-