1. 09 1月, 2014 2 次提交
  2. 18 10月, 2013 2 次提交
  3. 17 10月, 2013 6 次提交
    • A
      kvm: Add struct kvm arg to memslot APIs · 5587027c
      Aneesh Kumar K.V 提交于
      We will use that in the later patch to find the kvm ops handler
      Signed-off-by: NAneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      5587027c
    • A
      kvm: powerpc: book3s: Support building HV and PR KVM as module · 2ba9f0d8
      Aneesh Kumar K.V 提交于
      Signed-off-by: NAneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
      [agraf: squash in compile fix]
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      2ba9f0d8
    • A
      kvm: powerpc: book3s: Add is_hv_enabled to kvmppc_ops · 699cc876
      Aneesh Kumar K.V 提交于
      This help us to identify whether we are running with hypervisor mode KVM
      enabled. The change is needed so that we can have both HV and PR kvm
      enabled in the same kernel.
      
      If both HV and PR KVM are included, interrupts come in to the HV version
      of the kvmppc_interrupt code, which then jumps to the PR handler,
      renamed to kvmppc_interrupt_pr, if the guest is a PR guest.
      
      Allowing both PR and HV in the same kernel required some changes to
      kvm_dev_ioctl_check_extension(), since the values returned now can't
      be selected with #ifdefs as much as previously. We look at is_hv_enabled
      to return the right value when checking for capabilities.For capabilities that
      are only provided by HV KVM, we return the HV value only if
      is_hv_enabled is true. For capabilities provided by PR KVM but not HV,
      we return the PR value only if is_hv_enabled is false.
      
      NOTE: in later patch we replace is_hv_enabled with a static inline
      function comparing kvm_ppc_ops
      Signed-off-by: NAneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      699cc876
    • A
      kvm: powerpc: Add kvmppc_ops callback · 3a167bea
      Aneesh Kumar K.V 提交于
      This patch add a new callback kvmppc_ops. This will help us in enabling
      both HV and PR KVM together in the same kernel. The actual change to
      enable them together is done in the later patch in the series.
      Signed-off-by: NAneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
      [agraf: squash in booke changes]
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      3a167bea
    • P
      KVM: PPC: Book3S PR: Better handling of host-side read-only pages · 93b159b4
      Paul Mackerras 提交于
      Currently we request write access to all pages that get mapped into the
      guest, even if the guest is only loading from the page.  This reduces
      the effectiveness of KSM because it means that we unshare every page we
      access.  Also, we always set the changed (C) bit in the guest HPTE if
      it allows writing, even for a guest load.
      
      This fixes both these problems.  We pass an 'iswrite' flag to the
      mmu.xlate() functions and to kvmppc_mmu_map_page() to indicate whether
      the access is a load or a store.  The mmu.xlate() functions now only
      set C for stores.  kvmppc_gfn_to_pfn() now calls gfn_to_pfn_prot()
      instead of gfn_to_pfn() so that it can indicate whether we need write
      access to the page, and get back a 'writable' flag to indicate whether
      the page is writable or not.  If that 'writable' flag is clear, we then
      make the host HPTE read-only even if the guest HPTE allowed writing.
      
      This means that we can get a protection fault when the guest writes to a
      page that it has mapped read-write but which is read-only on the host
      side (perhaps due to KSM having merged the page).  Thus we now call
      kvmppc_handle_pagefault() for protection faults as well as HPTE not found
      faults.  In kvmppc_handle_pagefault(), if the access was allowed by the
      guest HPTE and we thus need to install a new host HPTE, we then need to
      remove the old host HPTE if there is one.  This is done with a new
      function, kvmppc_mmu_unmap_page(), which uses kvmppc_mmu_pte_vflush() to
      find and remove the old host HPTE.
      
      Since the memslot-related functions require the KVM SRCU read lock to
      be held, this adds srcu_read_lock/unlock pairs around the calls to
      kvmppc_handle_pagefault().
      
      Finally, this changes kvmppc_mmu_book3s_32_xlate_pte() to not ignore
      guest HPTEs that don't permit access, and to return -EPERM for accesses
      that are not permitted by the page protections.
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      93b159b4
    • P
      KVM: PPC: Book3S: Add GET/SET_ONE_REG interface for VRSAVE · c0867fd5
      Paul Mackerras 提交于
      The VRSAVE register value for a vcpu is accessible through the
      GET/SET_SREGS interface for Book E processors, but not for Book 3S
      processors.  In order to make this accessible for Book 3S processors,
      this adds a new register identifier for GET/SET_ONE_REG, and adds
      the code to implement it.
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      c0867fd5
  4. 27 4月, 2013 3 次提交
    • P
      KVM: PPC: Book3S: Facilities to save/restore XICS presentation ctrler state · 8b78645c
      Paul Mackerras 提交于
      This adds the ability for userspace to save and restore the state
      of the XICS interrupt presentation controllers (ICPs) via the
      KVM_GET/SET_ONE_REG interface.  Since there is one ICP per vcpu, we
      simply define a new 64-bit register in the ONE_REG space for the ICP
      state.  The state includes the CPU priority setting, the pending IPI
      priority, and the priority and source number of any pending external
      interrupt.
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      8b78645c
    • B
      KVM: PPC: Book3S: Add kernel emulation for the XICS interrupt controller · bc5ad3f3
      Benjamin Herrenschmidt 提交于
      This adds in-kernel emulation of the XICS (eXternal Interrupt
      Controller Specification) interrupt controller specified by PAPR, for
      both HV and PR KVM guests.
      
      The XICS emulation supports up to 1048560 interrupt sources.
      Interrupt source numbers below 16 are reserved; 0 is used to mean no
      interrupt and 2 is used for IPIs.  Internally these are represented in
      blocks of 1024, called ICS (interrupt controller source) entities, but
      that is not visible to userspace.
      
      Each vcpu gets one ICP (interrupt controller presentation) entity,
      used to store the per-vcpu state such as vcpu priority, pending
      interrupt state, IPI request, etc.
      
      This does not include any API or any way to connect vcpus to their
      ICP state; that will be added in later patches.
      
      This is based on an initial implementation by Michael Ellerman
      <michael@ellerman.id.au> reworked by Benjamin Herrenschmidt and
      Paul Mackerras.
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      [agraf: fix typo, add dependency on !KVM_MPIC]
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      bc5ad3f3
    • B
      KVM: PPC: debug stub interface parameter defined · 092d62ee
      Bharat Bhushan 提交于
      This patch defines the interface parameter for KVM_SET_GUEST_DEBUG
      ioctl support. Follow up patches will use this for setting up
      hardware breakpoints, watchpoints and software breakpoints.
      
      Also kvm_arch_vcpu_ioctl_set_guest_debug() is brought one level below.
      This is because I am not sure what is required for book3s. So this ioctl
      behaviour will not change for book3s.
      Signed-off-by: NBharat Bhushan <bharat.bhushan@freescale.com>
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      092d62ee
  5. 17 4月, 2013 1 次提交
  6. 22 3月, 2013 1 次提交
  7. 06 10月, 2012 3 次提交
    • P
      KVM: PPC: Book3S: Get/set guest FP regs using the GET/SET_ONE_REG interface · a8bd19ef
      Paul Mackerras 提交于
      This enables userspace to get and set all the guest floating-point
      state using the KVM_[GS]ET_ONE_REG ioctls.  The floating-point state
      includes all of the traditional floating-point registers and the
      FPSCR (floating point status/control register), all the VMX/Altivec
      vector registers and the VSCR (vector status/control register), and
      on POWER7, the vector-scalar registers (note that each FP register
      is the high-order half of the corresponding VSR).
      
      Most of these are implemented in common Book 3S code, except for VSX
      on POWER7.  Because HV and PR differ in how they store the FP and VSX
      registers on POWER7, the code for these cases is not common.  On POWER7,
      the FP registers are the upper halves of the VSX registers vsr0 - vsr31.
      PR KVM stores vsr0 - vsr31 in two halves, with the upper halves in the
      arch.fpr[] array and the lower halves in the arch.vsr[] array, whereas
      HV KVM on POWER7 stores the whole VSX register in arch.vsr[].
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      [agraf: fix whitespace, vsx compilation]
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      a8bd19ef
    • P
      KVM: PPC: Book3S: Get/set guest SPRs using the GET/SET_ONE_REG interface · a136a8bd
      Paul Mackerras 提交于
      This enables userspace to get and set various SPRs (special-purpose
      registers) using the KVM_[GS]ET_ONE_REG ioctls.  With this, userspace
      can get and set all the SPRs that are part of the guest state, either
      through the KVM_[GS]ET_REGS ioctls, the KVM_[GS]ET_SREGS ioctls, or
      the KVM_[GS]ET_ONE_REG ioctls.
      
      The SPRs that are added here are:
      
      - DABR:  Data address breakpoint register
      - DSCR:  Data stream control register
      - PURR:  Processor utilization of resources register
      - SPURR: Scaled PURR
      - DAR:   Data address register
      - DSISR: Data storage interrupt status register
      - AMR:   Authority mask register
      - UAMOR: User authority mask override register
      - MMCR0, MMCR1, MMCRA: Performance monitor unit control registers
      - PMC1..PMC8: Performance monitor unit counter registers
      
      In order to reduce code duplication between PR and HV KVM code, this
      moves the kvm_vcpu_ioctl_[gs]et_one_reg functions into book3s.c and
      centralizes the copying between user and kernel space there.  The
      registers that are handled differently between PR and HV, and those
      that exist only in one flavor, are handled in kvmppc_[gs]et_one_reg()
      functions that are specific to each flavor.
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      [agraf: minimal style fixes]
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      a136a8bd
    • B
      KVM: PPC: booke: Add watchdog emulation · f61c94bb
      Bharat Bhushan 提交于
      This patch adds the watchdog emulation in KVM. The watchdog
      emulation is enabled by KVM_ENABLE_CAP(KVM_CAP_PPC_BOOKE_WATCHDOG) ioctl.
      The kernel timer are used for watchdog emulation and emulates
      h/w watchdog state machine. On watchdog timer expiry, it exit to QEMU
      if TCR.WRC is non ZERO. QEMU can reset/shutdown etc depending upon how
      it is configured.
      Signed-off-by: NLiu Yu <yu.liu@freescale.com>
      Signed-off-by: NScott Wood <scottwood@freescale.com>
      [bharat.bhushan@freescale.com: reworked patch]
      Signed-off-by: NBharat Bhushan <bharat.bhushan@freescale.com>
      [agraf: adjust to new request framework]
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      f61c94bb
  8. 08 4月, 2012 2 次提交
  9. 05 3月, 2012 4 次提交
  10. 27 12月, 2011 1 次提交
  11. 01 11月, 2011 1 次提交
  12. 12 7月, 2011 5 次提交
    • P
      KVM: PPC: Deliver program interrupts right away instead of queueing them · 3cf658b6
      Paul Mackerras 提交于
      Doing so means that we don't have to save the flags anywhere and gets
      rid of the last reference to to_book3s(vcpu) in arch/powerpc/kvm/book3s.c.
      
      Doing so is OK because a program interrupt won't be generated at the
      same time as any other synchronous interrupt.  If a program interrupt
      and an asynchronous interrupt (external or decrementer) are generated
      at the same time, the program interrupt will be delivered, which is
      correct because it has a higher priority, and then the asynchronous
      interrupt will be masked.
      
      We don't ever generate system reset or machine check interrupts to the
      guest, but if we did, then we would need to make sure they got delivered
      rather than the program interrupt.  The current code would be wrong in
      this situation anyway since it would deliver the program interrupt as
      well as the reset/machine check interrupt.
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      3cf658b6
    • P
      KVM: PPC: Split out code from book3s.c into book3s_pr.c · f05ed4d5
      Paul Mackerras 提交于
      In preparation for adding code to enable KVM to use hypervisor mode
      on 64-bit Book 3S processors, this splits book3s.c into two files,
      book3s.c and book3s_pr.c, where book3s_pr.c contains the code that is
      specific to running the guest in problem state (user mode) and book3s.c
      contains code which should apply to all Book 3S processors.
      
      In doing this, we abstract some details, namely the interrupt offset,
      updating the interrupt pending flag, and detecting if the guest is
      in a critical section.  These are all things that will be different
      when we use hypervisor mode.
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      f05ed4d5
    • P
      KVM: PPC: Move fields between struct kvm_vcpu_arch and kvmppc_vcpu_book3s · c4befc58
      Paul Mackerras 提交于
      This moves the slb field, which represents the state of the emulated
      SLB, from the kvmppc_vcpu_book3s struct to the kvm_vcpu_arch, and the
      hpte_hash_[v]pte[_long] fields from kvm_vcpu_arch to kvmppc_vcpu_book3s.
      This is in accord with the principle that the kvm_vcpu_arch struct
      represents the state of the emulated CPU, and the kvmppc_vcpu_book3s
      struct holds the auxiliary data structures used in the emulation.
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      c4befc58
    • P
      KVM: PPC: Fix machine checks on 32-bit Book3S · 149dbdb1
      Paul Mackerras 提交于
      Commit 69acc0d3ba ("KVM: PPC: Resolve real-mode handlers through
      function exports") resulted in vcpu->arch.trampoline_lowmem and
      vcpu->arch.trampoline_enter ending up with kernel virtual addresses
      rather than physical addresses.  This is OK on 64-bit Book3S machines,
      which ignore the top 4 bits of the effective address in real mode,
      but on 32-bit Book3S machines, accessing these addresses in real mode
      causes machine check interrupts, as the hardware uses the whole
      effective address as the physical address in real mode.
      
      This fixes the problem by using __pa() to convert these addresses
      to physical addresses.
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      149dbdb1
    • A
      KVM: PPC: Resolve real-mode handlers through function exports · a22a2dac
      Alexander Graf 提交于
      Up until now, Book3S KVM had variables stored in the kernel that a kernel module
      or the kvm code in the kernel could read from to figure out where some real mode
      helper functions are located.
      
      This is all unnecessary. The high bits of the EA get ignore in real mode, so we
      can just use the pointer as is. Also, it's a lot easier on relocations when we
      use the normal way of resolving the address to a function, instead of jumping
      through hoops.
      
      This patch fixes compilation with CONFIG_RELOCATABLE=y.
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      a22a2dac
  13. 20 5月, 2011 1 次提交
  14. 18 3月, 2011 1 次提交
  15. 12 1月, 2011 1 次提交
  16. 24 10月, 2010 6 次提交
    • A
      KVM: PPC: Implement Level interrupts on Book3S · 17bd1580
      Alexander Graf 提交于
      The current interrupt logic is just completely broken. We get a notification
      from user space, telling us that an interrupt is there. But then user space
      expects us that we just acknowledge an interrupt once we deliver it to the
      guest.
      
      This is not how real hardware works though. On real hardware, the interrupt
      controller pulls the external interrupt line until it gets notified that the
      interrupt was received.
      
      So in reality we have two events: pulling and letting go of the interrupt line.
      
      To maintain backwards compatibility, I added a new request for the pulling
      part. The letting go part was implemented earlier already.
      
      With this in place, we can now finally start guests that do not randomly stall
      and stop to work at random times.
      
      This patch implements above logic for Book3S.
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      17bd1580
    • A
      KVM: PPC: Don't put MSR_POW in MSR · 296c19d0
      Alexander Graf 提交于
      On Book3S a mtmsr with the MSR_POW bit set indicates that the OS is in
      idle and only needs to be waked up on the next interrupt.
      
      Now, unfortunately we let that bit slip into the stored MSR value which
      is not what the real CPU does, so that we ended up executing code like
      this:
      
      	r = mfmsr();
      	/* r containts MSR_POW */
      	mtmsr(r | MSR_EE);
      
      This obviously breaks, as we're going into idle mode in code sections that
      don't expect to be idling.
      
      This patch masks MSR_POW out of the stored MSR value on wakeup, making
      guests happy again.
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      296c19d0
    • A
      KVM: PPC: Update int_pending also on dequeue · 9ee18b1e
      Alexander Graf 提交于
      When having a decrementor interrupt pending, the dequeuing happens manually
      through an mtdec instruction. This instruction simply calls dequeue on that
      interrupt, so the int_pending hint doesn't get updated.
      
      This patch enables updating the int_pending hint also on dequeue, thus
      correctly enabling guests to stay in guest contexts more often.
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      9ee18b1e
    • A
      KVM: PPC: Put segment registers in shared page · df1bfa25
      Alexander Graf 提交于
      Now that the actual mtsr doesn't do anything anymore, we can move the sr
      contents over to the shared page, so a guest can directly read and write
      its sr contents from guest context.
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      df1bfa25
    • A
      KVM: PPC: Interpret SR registers on demand · 8e865178
      Alexander Graf 提交于
      Right now we're examining the contents of Book3s_32's segment registers when
      the register is written and put the interpreted contents into a struct.
      
      There are two reasons this is bad. For starters, the struct has worse real-time
      performance, as it occupies more ram. But the more important part is that with
      segment registers being interpreted from their raw values, we can put them in
      the shared page, allowing guests to mess with them directly.
      
      This patch makes the internal representation of SRs be u32s.
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      8e865178
    • A
      KVM: PPC: Don't flush PTEs on NX/RO hit · 2e602847
      Alexander Graf 提交于
      When hitting a no-execute or read-only data/inst storage interrupt we were
      flushing the respective PTE so we're sure it gets properly overwritten next.
      
      According to the spec, this is unnecessary though. The guest issues a tlbie
      anyways, so we're safe to just keep the PTE around and have it manually removed
      from the guest, saving us a flush.
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      2e602847