1. 30 1月, 2017 1 次提交
    • A
      stmmac: Discard masked flags in interrupt status register · 0a764db1
      Alexey Brodkin 提交于
      DW GMAC databook says the following about bits in "Register 15 (Interrupt
      Mask Register)":
      --------------------------->8-------------------------
      When set, this bit __disables_the_assertion_of_the_interrupt_signal__
      because of the setting of XXX bit in Register 14 (Interrupt
      Status Register).
      --------------------------->8-------------------------
      
      In fact even if we mask one bit in the mask register it doesn't prevent
      corresponding bit to appear in the status register, it only disables
      interrupt generation for corresponding event.
      
      But currently we expect a bit different behavior: status bits to be in
      sync with their masks, i.e. if mask for bit A is set in the mask
      register then bit A won't appear in the interrupt status register.
      
      This was proven to be incorrect assumption, see discussion here [1].
      That misunderstanding causes unexpected behaviour of the GMAC, for
      example we were happy enough to just see bogus messages about link
      state changes.
      
      So from now on we'll be only checking bits that really may trigger an
      interrupt.
      
      [1] https://lkml.org/lkml/2016/11/3/413Signed-off-by: NAlexey Brodkin <abrodkin@synopsys.com>
      Cc: Giuseppe Cavallaro <peppe.cavallaro@st.com>
      Cc: Fabrice Gasnier <fabrice.gasnier@st.com>
      Cc: Joachim Eastwood <manabian@gmail.com>
      Cc: Phil Reid <preid@electromag.com.au>
      Cc: David Miller <davem@davemloft.net>
      Cc: Alexandre Torgue <alexandre.torgue@gmail.com>
      Cc: Vineet Gupta <vgupta@synopsys.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      0a764db1
  2. 28 1月, 2017 3 次提交
  3. 27 1月, 2017 8 次提交
  4. 26 1月, 2017 20 次提交
  5. 25 1月, 2017 8 次提交