Add support for the rk3399 excavator main board.
This board works in a combination with the sapphire SOM.

This board have been sold as the rk3399 evaluation board for commercial customers.
You can get more info from below link:
http://opensource.rock-chips.com/wiki_Excavator_sapphire_boardSigned-off-by: NJacob Chen <jacob-chen@iotwrt.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

Add support for the rk3399 sapphire SOM board.
This board works in a combination with the excavator main board.

You can get more info from below link:
http://opensource.rock-chips.com/wiki_Excavator_sapphire_boardSigned-off-by: NJacob Chen <jacob-chen@iotwrt.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

Add an hdmi node, and also add hdmi endpoints to vopb and vopl
output port nodes.
Signed-off-by: NJacob Chen <jacob-chen@iotwrt.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

Add an mipi node, and also add mipi endpoints to vopb and vopl
output port nodes.
Signed-off-by: NJacob Chen <jacob-chen@iotwrt.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

Add an edp node, and also add edp endpoints to vopb and vopl
output port nodes.
Signed-off-by: NYakir Yang <ykk@rock-chips.com>
Signed-off-by: NCaesar Wang <wxt@rock-chips.com>
Signed-off-by: NJacob Chen <jacob-chen@iotwrt.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

1. add pd node for RK3399 Soc
2. create power domain tree
3. add qos node for domain
Signed-off-by: NElaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: NCaesar Wang <wxt@rock-chips.com>
Signed-off-by: NJacob Chen <jacob-chen@iotwrt.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

Add devicetree nodes for rk3399 VOP (Video Output Processors), and the
top level display-subsystem root node.

Later patches add endpoints (eDP, HDMI, MIPI, etc) that attach to the
VOPs' output ports.
Signed-off-by: NMark Yao <mark.yao@rock-chips.com>
Signed-off-by: NYakir Yang <ykk@rock-chips.com>
Signed-off-by: NCaesar Wang <wxt@rock-chips.com>
Signed-off-by: NJacob Chen <jacob-chen@iotwrt.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

Add opp tables for cpu cluster0 and cluster1 by including
rk3399-opp.dtsi.
Signed-off-by: NJianqun Xu <jay.xu@rock-chips.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

This patch adds basic OPP entries for RK3328 SoC.
Signed-off-by: NFinley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

This patch updates the dynamic-power-coefficient for big cluster on
rk3399 SoCs.

The dynamic power consumption of the CPU is proportional to the square of
the Voltage (V) and the clock frequency (f). The coefficient is used to
calculate the dynamic power as below -
Pdyn = dynamic-power-coefficient * V^2 * f
Where Voltage is in uV, frequency is in MHz.

As the following is the tested data on rk3399's big cluster.
frequency(MHz)  Voltage(V)  Current(mA) Dynamic-power-coefficient
24              0.8         15
48              0.8         23          ~417
96              0.8         40          ~443
216             0.8         82          ~438
312             0.8         115         ~430
408             0.8         150         ~455
So the dynamic-power-coefficient average value is about 436.
Signed-off-by: NCaesar Wang <wxt@rock-chips.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

This patch add the spdif dt node for rk3328.
Signed-off-by: NSugar Zhang <sugar.zhang@rock-chips.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

This patch add the spdif dt node for rk3368 soc.
Signed-off-by: NSugar Zhang <sugar.zhang@rock-chips.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

This allows basic support for SD highspeed cards but no UHS-I mode
got ready due to the propagated defer-probe error from RK805.

Cc: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: NShawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

Add the core grf subnode for the io-domain controller.
Signed-off-by: NDavid Wu <david.wu@rock-chips.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

Kill these two pinctrl reference totally from rk3399 as it
never work indeed.
Signed-off-by: NShawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

pcie_clkreqn actually doesn't work at all, so replace it with
pcie_clkreqn_cpm.
Signed-off-by: NShawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

This patch enables the gpu and adds the mali-supply power for RK3399-GRU
devices.
Signed-off-by: NCaesar Wang <wxt@rock-chips.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

Add Mali GPU device tree node for the RK3399 SoCs, with devfreq
opp table.

RK3399 and RK3399-OP1 SoCs have a different recommendation table with
gpu opp. Also, the ARM's mali driver found on
https://developer.arm.com/products/software/mali-drivers/midgard-kernel.
Signed-off-by: NCaesar Wang <wxt@rock-chips.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

keep-power-in-suspend was invented for SDIO only, so it should
not be used for eMMC node.
Signed-off-by: NShawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

We deprecated the "num-slots" property now and plan to get
rid of it finally. Just move a step to cleanup it from DT.
Signed-off-by: NShawn Lin <shawn.lin@rock-chips.com>
Reviewed-by: NJaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

pcie_clkreqn actually doesn't work at all, so replace it with
pcie_clkreqn_cpm.
Signed-off-by: NShawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

The SdioAudio power domain includes the i2s/spdif/spi5/sdio.

So this patch adds the pd control for rk3399 i2s/spdif/spi5/sdio, in order
to save more power consumption.
Signed-off-by: NCaesar Wang <wxt@rock-chips.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

Rockchip's RK3328 evaluation board has one usb2 otg controller
and one usb2 host controller which consist of EHCI and OHCI.
Each usb controller connects with one usb2 phy port through
UTMI+ interface. Let's enable them to support usb2 on RK3328
evaluation board.
Signed-off-by: NWilliam Wu <william.wu@rock-chips.com>
[restructured enablement of u2phy subnodes]
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

This patch adds usb2 otg/host controllers and phys nodes
for Rockchip RK3328 SoCs.
Signed-off-by: NWilliam Wu <william.wu@rock-chips.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

Provide the dynamic power coefficient of the big and little CPU
clusters. These numbers are currently in use on the Samsung Chromebook
Plus ("Kevin").

The power allocator thermal governor doesn't know how to do anything if
it doesn't get power parameters from its cooling devices (in this case,
CPUfreq). So this effectively enables the power-allocator governor.
Signed-off-by: NBrian Norris <briannorris@chromium.org>
[set the property in each core node]
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

The Gru device tree currently contains entries for the regulators
ppvar_bigcpu, ppvar_litcpu, ppvar_gpu and ppvar_centerlogic; however,
the regulators have not been enabled, due to the lack of binding and driver
support for keeping the over-voltage protection (OVP) at bay and
preventing unintended regulator shutdowns on voltage downshifts.

Now, the vctrl regulator driver has been merged, along with new bindings
for asymmetric settling time. The driver is OVP aware, it splits larger
voltage decreases in multiple steps when necessary and adds required
delays.

This change renames each of the aforementioned regulators to
<orig_name>_pwm and adds a new vctrl regulator named <orig_name>.
The vctrl regulators use the voltage of their corresponding PWM regulator
as control voltage. The OVP related values are empirical and stem from
the Chrome OS kernel tree.
Signed-off-by: NMatthias Kaehlcke <mka@chromium.org>
Signed-off-by: NBrian Norris <briannorris@chromium.org>
[fixed node names and parent supplies of gpu and centerlogic]
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

Gru derivatives besides Kevin have slightly different voltage ranges for
their CPU regulators. Let's keep the base Gru file accurate and let
Kevin override.
Signed-off-by: NMatthias Kaehlcke <mka@chromium.org>
Signed-off-by: NBrian Norris <briannorris@chromium.org>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

replace all occurrences of sdmcc with sdmmc in the arm64 rockchip
devicetree files.
Signed-off-by: NKlaus Goger <klaus.goger@theobroma-systems.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

Contrary to popular belief, PPIs connected to a GICv3 to not have
an affinity field similar to that of GICv2. That is consistent
with the fact that GICv3 is designed to accomodate thousands of
CPUs, and fitting them as a bitmap in a byte is... difficult.

Fixes: adbc3695 ("arm64: dts: add the Marvell Armada 3700 family and
a development board")
Cc: <stable@vger.kernel.org>
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>
Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>

This reverts commits 2c0cba48 ("arm: sun8i: sunxi-h3-h5: Add dt node
for the syscon control module") to 2428fd0f ("arm64: defconfig: Enable
dwmac-sun8i driver on defconfig") and 3432a86e ("arm: sun8i:
orangepipc: use internal phy-mode") to 5a79b4f2 ("arm: sun8i:
orangepi-2: use internal phy-mode") that should be merged
through the arm-soc tree, and end up in merge conflicts and build failures.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

As I found by chance while merging another patch, the usage of
a dma-mask in this DT node is wrong for multiple reasons:

- dma-masks are a Linux specific concept, not a general
  hardware feature
- In DT, we use the "dma-ranges" property to describe how DMA
  addresses related between devices.
- The 40-bit mask appears to be completely unnecessary here, as
  the SoC cannot address that much memory anyway, so simply
  asking for a 64-bit mask (as supported by the device) should
  succeed anyway.

The patch to remove the parsing of the property is getting merged
through the crypto tree.
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

This resolves a build error in the next/dt branch:

In file included from arch/arm64/boot/dts/mediatek/mt6797-evb.dts:16:0:
arch/arm64/boot/dts/mediatek/mt6797.dtsi:15:10: fatal error: dt-bindings/power/mt6797-power.h: No such file or directory

003f5d0c ("arm64: dts: mediatek: add clk and scp nodes for MT6797")
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

Add support for the CC  board from Shenzhen Libre Technology
More information about the board are available here:

https://libre.computer/blog/

Cc: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: NJerome Brunet <jbrunet@baylibre.com>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

This commit modifies the Marvell EBU Armada 7K and 8K Device Tree files
to describe the ICU and GICP units, and use ICU interrupts for all
devices in the CP110 blocks.
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>

Compiling the DT file with W=1, DTC warns like follows:

Warning (unit_address_vs_reg): Node /opp_table0/opp@1000000000 has a
unit name, but no reg property

Fix this by replacing '@' with '-' as the OPP nodes will never have a
"reg" property.
Reported-by: NKrzysztof Kozlowski <krzk@kernel.org>
Reported-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Suggested-by: NMark Rutland <mark.rutland@arm.com>
Signed-off-by: NViresh Kumar <viresh.kumar@linaro.org>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>

Enable gpio support for CP and AP on the Marvell Armada 7K/8K SoCs.

The Armada 8K has two CP110 blocks, each having two GPIO controllers.
However, in each CP110 block, one of the GPIO controller cannot be
used: in the master CP110, only the second GPIO controller can be used,
while on the slave CP110, only the first GPIO controller can be used.

On the other side, the Armada 7K has only one CP110, but both its GPIO
controllers can be used.

For this reason, the GPIO controllers are marked as "disabled" in the
armada-cp110-master.dtsi and armada-cp110-slave.dtsi files, and only
enabled in the per-SoC dtsi files.
Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>

Enable pinctrl support for CP and AP on the Armada 7K/8K SoCs.

The CP master being different between Armada 7k and Armada 8k. This
commit introduces the intermediates files armada-70x0.dtsi and
armada-80x0.dtsi.

These new files will provide different compatible strings depending of
the SoC family. They will also be the location for the pinmux
configuration at the SoC level.
Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>

The new binding for the system controller on cp110 moved the clock
controller into a subnode. This preliminary step will allow to add gpio
and pinctrl subnodes.
Reviewed-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>

The *-clock-output-names of the cp110-system-controller0 node are not
used anymore, so remove them.
Reviewed-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>

New bindings are used for the system controller on the ap806, which
means all clock properties must be converted. Use the new bindings in
the xor nodes.
Signed-off-by: NAntoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>