- 06 3月, 2015 1 次提交
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由 Yingjoe Chen 提交于
MediaTek SoC expect to work with a pinctrl driver. Select PINCTRL if ARCH_MEDIATEK is selected. Signed-off-by: NYingjoe Chen <yingjoe.chen@mediatek.com> Signed-off-by: NMatthias Brugger <matthias.bgg@gmail.com>
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- 30 1月, 2015 1 次提交
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由 Paul Walmsley 提交于
Paul Bolle pointed out that commit d035fdfa ("arm64: Add Tegra132 support") included two Kconfig symbols that are now no-ops: USB_ARCH_HAS_EHCI and HAVE_SMP. So, drop the two symbols. This second version corrects a thinko in Paul Bolle's E-mail address. Signed-off-by: NPaul Walmsley <paul@pwsan.com> Cc: Paul Walmsley <pwalmsley@nvidia.com> Cc: Allen Martin <amartin@nvidia.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will.deacon@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Paul Bolle <pebolle@tiscali.nl> Signed-off-by: NOlof Johansson <olof@lixom.net>
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- 28 1月, 2015 2 次提交
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由 Olof Johansson 提交于
Signed-off-by: NOlof Johansson <olof@lixom.net>
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由 Bhupesh Sharma 提交于
This patch adds support for FSL's LS2085A SoC in the arm64 Kconfig and defconfig files. Signed-off-by: NBhupesh Sharma <bhupesh.sharma@freescale.com> Signed-off-by: NArnab Basu <arnab_basu@rocketmail.com> Signed-off-by: NOlof Johansson <olof@lixom.net>
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- 27 1月, 2015 1 次提交
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由 Lorenzo Pieralisi 提交于
ARM64_CPU_SUSPEND config option was introduced to make code providing context save/restore selectable only on platforms requiring power management capabilities. Currently ARM64_CPU_SUSPEND depends on the PM_SLEEP config option which in turn is set by the SUSPEND config option. The introduction of CPU_IDLE for arm64 requires that code configured by ARM64_CPU_SUSPEND (context save/restore) should be compiled in in order to enable the CPU idle driver to rely on CPU operations carrying out context save/restore. The ARM64_CPUIDLE config option (ARM64 generic idle driver) is therefore forced to select ARM64_CPU_SUSPEND, even if there may be (ie PM_SLEEP) failed dependencies, which is not a clean way of handling the kernel configuration option. For these reasons, this patch removes the ARM64_CPU_SUSPEND config option and makes the context save/restore dependent on CPU_PM, which is selected whenever either SUSPEND or CPU_IDLE are configured, cleaning up dependencies in the process. This way, code previously configured through ARM64_CPU_SUSPEND is compiled in whenever a power management subsystem requires it to be present in the kernel (SUSPEND || CPU_IDLE), which is the behaviour expected on ARM64 kernels. The cpu_suspend and cpu_init_idle CPU operations are added only if CPU_IDLE is selected, since they are CPU_IDLE specific methods and should be grouped and defined accordingly. PSCI CPU operations are updated to reflect the introduced changes. Signed-off-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Will Deacon <will.deacon@arm.com> Cc: Krzysztof Kozlowski <k.kozlowski@samsung.com> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Mark Rutland <mark.rutland@arm.com> Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
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- 26 1月, 2015 1 次提交
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由 Eddie Huang 提交于
Add MT8173 arm64 Kconfig and defconfig files Signed-off-by: NEddie Huang <eddie.huang@mediatek.com> Acked-by: Arnd Bergmann <arnd at arndb.de> Signed-off-by: NMatthias Brugger <matthias.bgg@gmail.com>
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- 24 1月, 2015 1 次提交
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由 Suzuki K. Poulose 提交于
Emulate deprecated 'setend' instruction for AArch32 bit tasks. setend [le/be] - Sets the endianness of EL0 On systems with CPUs which support mixed endian at EL0, the hardware support for the instruction can be enabled by setting the SCTLR_EL1.SED bit. Like the other emulated instructions it is controlled by an entry in /proc/sys/abi/. For more information see : Documentation/arm64/legacy_instructions.txt The instruction is emulated by setting/clearing the SPSR_EL1.E bit, which will be reflected in the PSTATE.E in AArch32 context. This patch also restores the native endianness for the execution of signal handlers, since the process could have changed the endianness. Note: All CPUs on the system must have mixed endian support at EL0. Once the handler is registered, hotplugging a CPU which doesn't support mixed endian, could lead to unexpected results/behavior in applications. Signed-off-by: NSuzuki K. Poulose <suzuki.poulose@arm.com> Cc: Will Deacon <will.deacon@arm.com> Cc: Punit Agrawal <punit.agrawal@arm.com> Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
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- 23 1月, 2015 1 次提交
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由 Paul Walmsley 提交于
Add basic Kbuild support for the Tegra SoC family, and specifically, the Tegra132 SoC. Tegra132 pairs the NVIDIA Denver CPU complex with the SoC integration of Tegra124 - hence the use of ARCH_TEGRA and the Tegra124 pinctrl option. This patch was based on a patch originally written by Allen Martin <amartin@nvidia.com>. Signed-off-by: NPaul Walmsley <paul@pwsan.com> Cc: Paul Walmsley <pwalmsley@nvidia.com> Cc: Allen Martin <amartin@nvidia.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will.deacon@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Signed-off-by: NThierry Reding <treding@nvidia.com>
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- 19 1月, 2015 1 次提交
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由 Will Deacon 提交于
The ARM SMMU can walk LPAE page tables, so make use of the generic allocator. Signed-off-by: NWill Deacon <will.deacon@arm.com>
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- 23 12月, 2014 1 次提交
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由 Yalin Wang 提交于
This patch add bitrev.h file to support rbit instruction, so that we can do bitrev operation by hardware. Signed-off-by: NYalin Wang <yalin.wang@sonymobile.com> Acked-by: NWill Deacon <will.deacon@arm.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 22 12月, 2014 1 次提交
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由 Alim Akhtar 提交于
This patch adds the necessary Kconfig entries to enable support for the ARMv8 based exynos7 SoC. It also enables RTC, WDT and Pinctrl for exynos7 SoC. Signed-off-by: NAlim Akhtar <alim.akhtar@samsung.com> Signed-off-by: NNaveen Krishna Ch <naveenkrishna.ch@gmail.com> Signed-off-by: NAbhilash Kesavan <a.kesavan@samsung.com> Reviewed-by: NThomas Abraham <thomas.ab@samsung.com> Tested-by: NThomas Abraham <thomas.ab@samsung.com> Cc: Rob Herring <robh@kernel.org> Cc: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: NKukjin Kim <kgene@kernel.org>
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- 14 12月, 2014 1 次提交
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由 Riku Voipio 提交于
Following the suggestions from Andrew Morton and Stephen Rothwell, Dont expand the ARCH list in kernel/gcov/Kconfig. Instead, define a ARCH_HAS_GCOV_PROFILE_ALL bool which architectures can enable. set ARCH_HAS_GCOV_PROFILE_ALL on Architectures where it was previously allowed + ARM64 which I tested. Signed-off-by: NRiku Voipio <riku.voipio@linaro.org> Cc: Peter Oberparleiter <oberpar@linux.vnet.ibm.com> Cc: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: NAndrew Morton <akpm@linux-foundation.org> Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
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- 28 11月, 2014 2 次提交
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由 Suravee Suthikulpanit 提交于
Initial revision of device tree for AMD Seattle Development platform. Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Will Deacon <will.deacon@arm.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: NSuravee Suthikulpanit <Suravee.Suthikulpanit@amd.com> Signed-off-by: NThomas Lendacky <Thomas.Lendacky@amd.com> Signed-off-by: NJoel Schopp <Joel.Schopp@amd.com> Signed-off-by: NArnd Bergmann <arnd@arndb.de>
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由 AKASHI Takahiro 提交于
secure_computing() is called first in syscall_trace_enter() so that a system call will be aborted quickly without doing succeeding syscall tracing if seccomp rules want to deny that system call. On compat task, syscall numbers for system calls allowed in seccomp mode 1 are different from those on normal tasks, and so _NR_seccomp_xxx_32's need to be redefined. Signed-off-by: NAKASHI Takahiro <takahiro.akashi@linaro.org> Signed-off-by: NWill Deacon <will.deacon@arm.com>
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- 26 11月, 2014 3 次提交
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由 Suravee Suthikulpanit 提交于
ARM GICv2m specification extends GICv2 to support MSI(-X) with a new register frame. This allows a GICv2 based system to support MSI with minimal changes. Signed-off-by: NSuravee Suthikulpanit <Suravee.Suthikulpanit@amd.com> [maz: converted the driver to use stacked irq domains, updated changelog] Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com> Link: https://lkml.kernel.org/r/1416941243-7181-2-git-send-email-marc.zyngier@arm.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>
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由 Marc Zyngier 提交于
Get the show on the road... Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com> Link: https://lkml.kernel.org/r/1416839720-18400-13-git-send-email-marc.zyngier@arm.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>
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由 Thierry Reding 提交于
Rather than duplicate the ARM_AMBA Kconfig symbol in both 32-bit and 64-bit ARM architectures, move the common definition to drivers/amba where dependent drivers will be located. Signed-off-by: NThierry Reding <treding@nvidia.com>
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- 25 11月, 2014 1 次提交
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由 Andre Przywara 提交于
Not all of the errata we have workarounds for apply necessarily to all SoCs, so people compiling a kernel for one very specific SoC may not need to patch the kernel. Introduce a new submenu in the "Platform selection" menu to allow people to turn off certain bugs if they are not affected. By default all of them are enabled. Normal users or distribution kernels shouldn't bother to deselect any bugs here, since the alternatives framework will take care of patching them in only if needed. Signed-off-by: NAndre Przywara <andre.przywara@arm.com> [will: moved kconfig menu under `Kernel Features'] Signed-off-by: NWill Deacon <will.deacon@arm.com>
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- 21 11月, 2014 4 次提交
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由 Will Deacon 提交于
Having the instruction emulation submenu underneath "platform selection" is a great way to hide options we don't want people to use, but somewhat confusing when you stumble across it there. Move the menuconfig option underneath "kernel features", where it makes a bit more sense. Signed-off-by: NWill Deacon <will.deacon@arm.com>
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由 Punit Agrawal 提交于
The CP15 barrier instructions (CP15ISB, CP15DSB and CP15DMB) are deprecated in the ARMv7 architecture, superseded by ISB, DSB and DMB instructions respectively. Some implementations may provide the ability to disable the CP15 barriers by disabling the CP15BEN bit in SCTLR_EL1. If not enabled, the encodings for these instructions become undefined. To support legacy software using these instructions, this patch register hooks to - * emulate CP15 barriers and warn the user about their use * toggle CP15BEN in SCTLR_EL1 Signed-off-by: NPunit Agrawal <punit.agrawal@arm.com> Reviewed-by: NCatalin Marinas <catalin.marinas@arm.com> Signed-off-by: NWill Deacon <will.deacon@arm.com>
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由 Punit Agrawal 提交于
The SWP instruction was deprecated in the ARMv6 architecture. The ARMv7 multiprocessing extensions mandate that SWP/SWPB instructions are treated as undefined from reset, with the ability to enable them through the System Control Register SW bit. With ARMv8, the option to enable these instructions through System Control Register was dropped as well. To support legacy applications using these instructions, port the emulation of the SWP and SWPB instructions from the arm port to arm64. Reviewed-by: NCatalin Marinas <catalin.marinas@arm.com> Signed-off-by: NPunit Agrawal <punit.agrawal@arm.com> Signed-off-by: NWill Deacon <will.deacon@arm.com>
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由 Punit Agrawal 提交于
Typically, providing support for legacy instructions requires emulating the behaviour of instructions whose encodings have become undefined. If the instructions haven't been removed from the architecture, there maybe an option in the implementation to turn on/off the support for these instructions. Create common infrastructure to support legacy instruction emulation. In addition to emulation, also provide an option to support hardware execution when supported. The default execution mode (one of undef, emulate, hw exeuction) is dependent on the state of the instruction (deprecated or obsolete) in the architecture and can specified at the time of registering the instruction handlers. The runtime state of the emulation can be controlled by writing to individual nodes in sysctl. The expected default behaviour is documented as part of this patch. Reviewed-by: NCatalin Marinas <catalin.marinas@arm.com> Signed-off-by: NPunit Agrawal <punit.agrawal@arm.com> Signed-off-by: NWill Deacon <will.deacon@arm.com>
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- 19 11月, 2014 1 次提交
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由 Arnd Bergmann 提交于
Patch 09a57239 ("arm64: Use include/asm-generic/io.h") correctly removed the GENERIC_IOMAP selection from ARM64, which is not needed on architectures that have memory-mapped PCI I/O space, however we now lack a pci_iomap() function. Fortunately, there is already a generic implementation for this case, so we just need to select GENERIC_PCI_IOMAP to make it all work. Signed-off-by: NArnd Bergmann <arnd@arndb.de> Fixes: 09a57239 ("arm64: Use include/asm-generic/io.h")
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- 10 11月, 2014 1 次提交
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由 Thierry Reding 提交于
Include the generic I/O header file so that duplicate implementations can be removed. This will also help to establish consistency across more architectures regarding which accessors they support. Acked-by: NCatalin Marinas <catalin.marinas@arm.com> Signed-off-by: NThierry Reding <treding@nvidia.com>
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- 07 11月, 2014 1 次提交
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由 Steve Capper 提交于
The arm64 architecture has the ability to exclusively load and store a pair of registers from an address (ldxp/stxp). Also the SLUB can take advantage of a cmpxchg_double implementation to avoid taking some locks. This patch provides an implementation of cmpxchg_double for 64-bit pairs, and activates the logic required for the SLUB to use these functions (HAVE_ALIGNED_STRUCT_PAGE and HAVE_CMPXCHG_DOUBLE). Also definitions of this_cpu_cmpxchg_8 and this_cpu_cmpxchg_double_8 are wired up to cmpxchg_local and cmpxchg_double_local (rather than the stock implementations that perform non-atomic operations with interrupts disabled) as they are used by the SLUB. On a Juno platform running on only the A57s I get quite a noticeable performance improvement with 5 runs of hackbench on v3.17: Baseline | With Patch -----------------+----------- Mean 119.2312 | 106.1782 StdDev 0.4919 | 0.4494 (times taken to complete `./hackbench 100 process 1000', in seconds) Signed-off-by: NSteve Capper <steve.capper@linaro.org> Signed-off-by: NWill Deacon <will.deacon@arm.com>
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- 05 11月, 2014 1 次提交
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由 Yi Li 提交于
SMBIOS is important for server hardware vendors. It implements a spec for providing descriptive information about the platform. Things like serial numbers, physical layout of the ports, build configuration data, and the like. Signed-off-by: NYi Li <yi.li@linaro.org> Tested-by: NSuravee Suthikulpanit <suravee.suthikulpanit@amd.com> Tested-by: NLeif Lindholm <leif.lindholm@linaro.org> Signed-off-by: NArd Biesheuvel <ard.biesheuvel@linaro.org>
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- 24 10月, 2014 1 次提交
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由 Arun Chandran 提交于
When user asks to turn off ASLR by writing "0" to /proc/sys/kernel/randomize_va_space there should not be any randomization to mmap base, stack, VDSO, libs, text and heap Currently arm64 violates this behavior by randomising text. Fix this by defining a constant ELF_ET_DYN_BASE. The randomisation of mm->mmap_base is done by setup_new_exec -> arch_pick_mmap_layout -> mmap_base -> mmap_rnd. Signed-off-by: NArun Chandran <achandran@mvista.com> Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
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- 21 10月, 2014 1 次提交
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由 Christoffer Dall 提交于
Now when KVM has been reworked to support 48-bits host VA space, we can allow systems to be configured with this option. However, the ARM SMMU driver also needs to be tweaked for 48-bit support so only allow the config option to be set when not including support for theSMMU. Signed-off-by: NChristoffer Dall <christoffer.dall@linaro.org> Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
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- 10 10月, 2014 3 次提交
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由 Steve Capper 提交于
Activate the RCU fast_gup for ARM64. We also need to force THP splits to broadcast an IPI s.t. we block in the fast_gup page walker. As THP splits are comparatively rare, this should not lead to a noticeable performance degradation. Some pre-requisite functions pud_write and pud_page are also added. [akpm@linux-foundation.org: coding-style fixes] Signed-off-by: NSteve Capper <steve.capper@linaro.org> Tested-by: NDann Frazier <dann.frazier@canonical.com> Acked-by: NCatalin Marinas <catalin.marinas@arm.com> Cc: Hugh Dickins <hughd@google.com> Cc: Russell King <rmk@arm.linux.org.uk> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Mel Gorman <mel@csn.ul.ie> Cc: Will Deacon <will.deacon@arm.com> Cc: Christoffer Dall <christoffer.dall@linaro.org> Cc: Andrea Arcangeli <aarcange@redhat.com> Signed-off-by: NAndrew Morton <akpm@linux-foundation.org> Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
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由 Steve Capper 提交于
In order to implement fast_get_user_pages we need to ensure that the page table walker is protected from page table pages being freed from under it. This patch enables HAVE_RCU_TABLE_FREE, any page table pages belonging to address spaces with multiple users will be call_rcu_sched freed. Meaning that disabling interrupts will block the free and protect the fast gup page walker. Signed-off-by: NSteve Capper <steve.capper@linaro.org> Tested-by: NDann Frazier <dann.frazier@canonical.com> Acked-by: NCatalin Marinas <catalin.marinas@arm.com> Cc: Hugh Dickins <hughd@google.com> Cc: Russell King <rmk@arm.linux.org.uk> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Mel Gorman <mel@csn.ul.ie> Cc: Will Deacon <will.deacon@arm.com> Cc: Christoffer Dall <christoffer.dall@linaro.org> Cc: Andrea Arcangeli <aarcange@redhat.com> Signed-off-by: NAndrew Morton <akpm@linux-foundation.org> Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
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由 Laura Abbott 提交于
Neither CMA nor noncoherent allocations support atomic allocations. Add a dedicated atomic pool to support this. Reviewed-by: NCatalin Marinas <catalin.marinas@arm.com> Signed-off-by: NLaura Abbott <lauraa@codeaurora.org> Cc: Arnd Bergmann <arnd@arndb.de> Cc: David Riley <davidriley@chromium.org> Cc: Olof Johansson <olof@lixom.net> Cc: Ritesh Harjain <ritesh.harjani@gmail.com> Cc: Russell King <linux@arm.linux.org.uk> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Will Deacon <will.deacon@arm.com> Signed-off-by: NAndrew Morton <akpm@linux-foundation.org> Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
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- 03 10月, 2014 1 次提交
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由 Julien Grall 提交于
The Xen ARM API is stable since Xen 4.4 and everything has been upstreamed in Linux for ARM and ARM64. Therefore we can drop "EXPERIMENTAL" from the Xen option in the both Kconfig. Signed-off-by: NJulien Grall <julien.grall@linaro.org> Cc: Russell King <linux@arm.linux.org.uk> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will.deacon@arm.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org
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- 02 10月, 2014 1 次提交
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由 Radha Mohan Chintakuntla 提交于
This introduces ARCH_THUNDER to enable soc specific drivers and dtb files. Signed-off-by: NRadha Mohan Chintakuntla <rchintakuntla@cavium.com> Signed-off-by: NRobert Richter <rrichter@cavium.com> Signed-off-by: NArnd Bergmann <arnd@arndb.de>
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- 01 10月, 2014 1 次提交
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由 Liviu Dudau 提交于
Use the generic PCI domain and OF functions to provide support for PCI on arm64. [bhelgaas: Change comments to use generic PCI, not just PCIe. Nothing at this level is PCIe-specific.] Signed-off-by: NLiviu Dudau <Liviu.Dudau@arm.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Acked-by: NCatalin Marinas <catalin.marinas@arm.com>
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- 23 9月, 2014 1 次提交
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由 Catalin Marinas 提交于
This reverts commit 668ebd10. ... because of lots of warnings during boot if Linux isn't started as an EFI application: WARNING: CPU: 4 PID: 1 at /work/Linux/linux-2.6-aarch64/drivers/firmware/dmi_scan.c:591 dmi_matches+0x10c/0x110() dmi check: not initialized yet. Modules linked in: CPU: 4 PID: 1 Comm: swapper/0 Not tainted 3.17.0-rc4+ #606 Call trace: [<ffffffc000087fb0>] dump_backtrace+0x0/0x124 [<ffffffc0000880e4>] show_stack+0x10/0x1c [<ffffffc0004d58f8>] dump_stack+0x74/0xb8 [<ffffffc0000ab640>] warn_slowpath_common+0x8c/0xb4 [<ffffffc0000ab6b4>] warn_slowpath_fmt+0x4c/0x58 [<ffffffc0003f2d7c>] dmi_matches+0x108/0x110 [<ffffffc0003f2da8>] dmi_check_system+0x24/0x68 [<ffffffc0006974c4>] atkbd_init+0x10/0x34 [<ffffffc0000814ac>] do_one_initcall+0x88/0x1a0 [<ffffffc00067aab4>] kernel_init_freeable+0x148/0x1e8 [<ffffffc0004d2c64>] kernel_init+0x10/0xd4 Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
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- 22 9月, 2014 1 次提交
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由 Yi Li 提交于
SMBIOS is important for server hardware vendors. It implements a spec for providing descriptive information about the platform. Things like serial numbers, physical layout of the ports, build configuration data, and the like. This has been tested by dmidecode and lshw tools. This patch adds the call to dmi_scan_machine() to arm64_enter_virtual_mode(), as that is the point where the EFI Configuration Tables are registered as being available. It needs to be in an early_initcall anyway as dmi_id_init(), which is an arch_initcall itself, depends on dmi_scan_machine() having been called already. Signed-off-by: NYi Li <yi.li@linaro.org> Signed-off-by: NArd Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
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- 08 9月, 2014 2 次提交
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由 Robert Richter 提交于
Raising the current maximum limit to 64. This is needed for Cavium's Thunder systems that will have at least 48 cores per die. The change keeps the current memory footprint in cpu mask structures. It does not break existing code. Setting the maximum to 64 cpus still boots systems with less cpus. Mark's Juno happily booted with a NR_CPUS=64 kernel. Tested on our Thunder system with 48 cores. We could see interrupts to all cores. Cc: Radha Mohan Chintakuntla <rchintakuntla@cavium.com> Cc: Mark Rutland <mark.rutland@arm.com> Acked-by: NArnd Bergmann <arnd@arndb.de> Signed-off-by: NRobert Richter <rrichter@cavium.com> Signed-off-by: NWill Deacon <will.deacon@arm.com>
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由 Zi Shen Lim 提交于
The JIT compiler emits A64 instructions. It supports eBPF only. Legacy BPF is supported thanks to conversion by BPF core. JIT is enabled in the same way as for other architectures: echo 1 > /proc/sys/net/core/bpf_jit_enable Or for additional compiler output: echo 2 > /proc/sys/net/core/bpf_jit_enable See Documentation/networking/filter.txt for more information. The implementation passes all 57 tests in lib/test_bpf.c on ARMv8 Foundation Model :) Also tested by Will on Juno platform. Signed-off-by: NZi Shen Lim <zlim.lnx@gmail.com> Acked-by: NAlexei Starovoitov <ast@plumgrid.com> Acked-by: NWill Deacon <will.deacon@arm.com> Signed-off-by: NWill Deacon <will.deacon@arm.com>
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- 03 9月, 2014 1 次提交
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由 Marc Zyngier 提交于
In order to limit code duplication, convert the architecture specific handle_IRQ to use the generic __handle_domain_irq function. Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com> Acked-by: NCatalin Marinas <catalin.marinas@arm.com> Link: https://lkml.kernel.org/r/1409047421-27649-3-git-send-email-marc.zyngier@arm.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>
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- 09 8月, 2014 1 次提交
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由 Laura Abbott 提交于
Rather than have architectures #define ARCH_HAS_SG_CHAIN in an architecture specific scatterlist.h, make it a proper Kconfig option and use that instead. At same time, remove the header files are are now mostly useless and just include asm-generic/scatterlist.h. [sfr@canb.auug.org.au: powerpc files now need asm/dma.h] Signed-off-by: NLaura Abbott <lauraa@codeaurora.org> Acked-by: Thomas Gleixner <tglx@linutronix.de> [x86] Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> [powerpc] Acked-by: NHeiko Carstens <heiko.carstens@de.ibm.com> Cc: Russell King <linux@arm.linux.org.uk> Cc: Tony Luck <tony.luck@intel.com> Cc: Fenghua Yu <fenghua.yu@intel.com> Cc: Paul Mackerras <paulus@samba.org> Cc: Ingo Molnar <mingo@redhat.com> Cc: "H. Peter Anvin" <hpa@zytor.com> Cc: "James E.J. Bottomley" <JBottomley@parallels.com> Cc: Martin Schwidefsky <schwidefsky@de.ibm.com> Signed-off-by: NStephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: NAndrew Morton <akpm@linux-foundation.org> Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
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