1. 06 3月, 2015 1 次提交
  2. 30 1月, 2015 1 次提交
    • P
      arm64: Kconfig: clean up two no-op Kconfig options from CONFIG_ARCH_TEGRA* · 0d2fdcd7
      Paul Walmsley 提交于
      Paul Bolle pointed out that commit
      d035fdfa ("arm64: Add Tegra132
      support") included two Kconfig symbols that are now no-ops:
      USB_ARCH_HAS_EHCI and HAVE_SMP.  So, drop the two symbols.
      
      This second version corrects a thinko in Paul Bolle's E-mail address.
      Signed-off-by: NPaul Walmsley <paul@pwsan.com>
      Cc: Paul Walmsley <pwalmsley@nvidia.com>
      Cc: Allen Martin <amartin@nvidia.com>
      Cc: Thierry Reding <treding@nvidia.com>
      Cc: Catalin Marinas <catalin.marinas@arm.com>
      Cc: Will Deacon <will.deacon@arm.com>
      Cc: Mark Rutland <mark.rutland@arm.com>
      Cc: Paul Bolle <pebolle@tiscali.nl>
      Signed-off-by: NOlof Johansson <olof@lixom.net>
      0d2fdcd7
  3. 28 1月, 2015 2 次提交
  4. 27 1月, 2015 1 次提交
    • L
      arm64: kernel: remove ARM64_CPU_SUSPEND config option · af3cfdbf
      Lorenzo Pieralisi 提交于
      ARM64_CPU_SUSPEND config option was introduced to make code providing
      context save/restore selectable only on platforms requiring power
      management capabilities.
      
      Currently ARM64_CPU_SUSPEND depends on the PM_SLEEP config option which
      in turn is set by the SUSPEND config option.
      
      The introduction of CPU_IDLE for arm64 requires that code configured
      by ARM64_CPU_SUSPEND (context save/restore) should be compiled in
      in order to enable the CPU idle driver to rely on CPU operations
      carrying out context save/restore.
      
      The ARM64_CPUIDLE config option (ARM64 generic idle driver) is therefore
      forced to select ARM64_CPU_SUSPEND, even if there may be (ie PM_SLEEP)
      failed dependencies, which is not a clean way of handling the kernel
      configuration option.
      
      For these reasons, this patch removes the ARM64_CPU_SUSPEND config option
      and makes the context save/restore dependent on CPU_PM, which is selected
      whenever either SUSPEND or CPU_IDLE are configured, cleaning up dependencies
      in the process.
      
      This way, code previously configured through ARM64_CPU_SUSPEND is
      compiled in whenever a power management subsystem requires it to be
      present in the kernel (SUSPEND || CPU_IDLE), which is the behaviour
      expected on ARM64 kernels.
      
      The cpu_suspend and cpu_init_idle CPU operations are added only if
      CPU_IDLE is selected, since they are CPU_IDLE specific methods and
      should be grouped and defined accordingly.
      
      PSCI CPU operations are updated to reflect the introduced changes.
      Signed-off-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
      Cc: Arnd Bergmann <arnd@arndb.de>
      Cc: Will Deacon <will.deacon@arm.com>
      Cc: Krzysztof Kozlowski <k.kozlowski@samsung.com>
      Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
      Cc: Mark Rutland <mark.rutland@arm.com>
      Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
      af3cfdbf
  5. 26 1月, 2015 1 次提交
  6. 24 1月, 2015 1 次提交
    • S
      arm64: Emulate SETEND for AArch32 tasks · 2d888f48
      Suzuki K. Poulose 提交于
      Emulate deprecated 'setend' instruction for AArch32 bit tasks.
      
      	setend [le/be] - Sets the endianness of EL0
      
      On systems with CPUs which support mixed endian at EL0, the hardware
      support for the instruction can be enabled by setting the SCTLR_EL1.SED
      bit. Like the other emulated instructions it is controlled by an entry in
      /proc/sys/abi/. For more information see :
      	Documentation/arm64/legacy_instructions.txt
      
      The instruction is emulated by setting/clearing the SPSR_EL1.E bit, which
      will be reflected in the PSTATE.E in AArch32 context.
      
      This patch also restores the native endianness for the execution of signal
      handlers, since the process could have changed the endianness.
      
      Note: All CPUs on the system must have mixed endian support at EL0. Once the
      handler is registered, hotplugging a CPU which doesn't support mixed endian,
      could lead to unexpected results/behavior in applications.
      Signed-off-by: NSuzuki K. Poulose <suzuki.poulose@arm.com>
      Cc: Will Deacon <will.deacon@arm.com>
      Cc: Punit Agrawal <punit.agrawal@arm.com>
      Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
      2d888f48
  7. 23 1月, 2015 1 次提交
    • P
      arm64: Add Tegra132 support · d035fdfa
      Paul Walmsley 提交于
      Add basic Kbuild support for the Tegra SoC family, and specifically,
      the Tegra132 SoC.  Tegra132 pairs the NVIDIA Denver CPU complex with
      the SoC integration of Tegra124 - hence the use of ARCH_TEGRA and the
      Tegra124 pinctrl option.
      
      This patch was based on a patch originally written by Allen Martin
      <amartin@nvidia.com>.
      Signed-off-by: NPaul Walmsley <paul@pwsan.com>
      Cc: Paul Walmsley <pwalmsley@nvidia.com>
      Cc: Allen Martin <amartin@nvidia.com>
      Cc: Thierry Reding <treding@nvidia.com>
      Cc: Catalin Marinas <catalin.marinas@arm.com>
      Cc: Will Deacon <will.deacon@arm.com>
      Cc: Mark Rutland <mark.rutland@arm.com>
      Signed-off-by: NThierry Reding <treding@nvidia.com>
      d035fdfa
  8. 19 1月, 2015 1 次提交
  9. 23 12月, 2014 1 次提交
  10. 22 12月, 2014 1 次提交
  11. 14 12月, 2014 1 次提交
  12. 28 11月, 2014 2 次提交
  13. 26 11月, 2014 3 次提交
  14. 25 11月, 2014 1 次提交
    • A
      arm64: protect alternatives workarounds with Kconfig options · c0a01b84
      Andre Przywara 提交于
      Not all of the errata we have workarounds for apply necessarily to all
      SoCs, so people compiling a kernel for one very specific SoC may not
      need to patch the kernel.
      Introduce a new submenu in the "Platform selection" menu to allow
      people to turn off certain bugs if they are not affected. By default
      all of them are enabled.
      Normal users or distribution kernels shouldn't bother to deselect any
      bugs here, since the alternatives framework will take care of
      patching them in only if needed.
      Signed-off-by: NAndre Przywara <andre.przywara@arm.com>
      [will: moved kconfig menu under `Kernel Features']
      Signed-off-by: NWill Deacon <will.deacon@arm.com>
      c0a01b84
  15. 21 11月, 2014 4 次提交
    • W
      arm64: kconfig: move emulation option under kernel features · 1b907f46
      Will Deacon 提交于
      Having the instruction emulation submenu underneath "platform selection"
      is a great way to hide options we don't want people to use, but somewhat
      confusing when you stumble across it there.
      
      Move the menuconfig option underneath "kernel features", where it makes
      a bit more sense.
      Signed-off-by: NWill Deacon <will.deacon@arm.com>
      1b907f46
    • P
      arm64: Emulate CP15 Barrier instructions · c852f320
      Punit Agrawal 提交于
      The CP15 barrier instructions (CP15ISB, CP15DSB and CP15DMB) are
      deprecated in the ARMv7 architecture, superseded by ISB, DSB and DMB
      instructions respectively. Some implementations may provide the
      ability to disable the CP15 barriers by disabling the CP15BEN bit in
      SCTLR_EL1. If not enabled, the encodings for these instructions become
      undefined.
      
      To support legacy software using these instructions, this patch
      register hooks to -
      * emulate CP15 barriers and warn the user about their use
      * toggle CP15BEN in SCTLR_EL1
      Signed-off-by: NPunit Agrawal <punit.agrawal@arm.com>
      Reviewed-by: NCatalin Marinas <catalin.marinas@arm.com>
      Signed-off-by: NWill Deacon <will.deacon@arm.com>
      c852f320
    • P
      arm64: Port SWP/SWPB emulation support from arm · bd35a4ad
      Punit Agrawal 提交于
      The SWP instruction was deprecated in the ARMv6 architecture. The
      ARMv7 multiprocessing extensions mandate that SWP/SWPB instructions
      are treated as undefined from reset, with the ability to enable them
      through the System Control Register SW bit. With ARMv8, the option to
      enable these instructions through System Control Register was dropped
      as well.
      
      To support legacy applications using these instructions, port the
      emulation of the SWP and SWPB instructions from the arm port to arm64.
      Reviewed-by: NCatalin Marinas <catalin.marinas@arm.com>
      Signed-off-by: NPunit Agrawal <punit.agrawal@arm.com>
      Signed-off-by: NWill Deacon <will.deacon@arm.com>
      bd35a4ad
    • P
      arm64: Add framework for legacy instruction emulation · 587064b6
      Punit Agrawal 提交于
      Typically, providing support for legacy instructions requires
      emulating the behaviour of instructions whose encodings have become
      undefined. If the instructions haven't been removed from the
      architecture, there maybe an option in the implementation to turn
      on/off the support for these instructions.
      
      Create common infrastructure to support legacy instruction
      emulation. In addition to emulation, also provide an option to support
      hardware execution when supported. The default execution mode (one of
      undef, emulate, hw exeuction) is dependent on the state of the
      instruction (deprecated or obsolete) in the architecture and
      can specified at the time of registering the instruction handlers. The
      runtime state of the emulation can be controlled by writing to
      individual nodes in sysctl. The expected default behaviour is
      documented as part of this patch.
      Reviewed-by: NCatalin Marinas <catalin.marinas@arm.com>
      Signed-off-by: NPunit Agrawal <punit.agrawal@arm.com>
      Signed-off-by: NWill Deacon <will.deacon@arm.com>
      587064b6
  16. 19 11月, 2014 1 次提交
    • A
      ARM64: use GENERIC_PCI_IOMAP · cb61f676
      Arnd Bergmann 提交于
      Patch 09a57239 ("arm64: Use include/asm-generic/io.h") correctly
      removed the GENERIC_IOMAP selection from ARM64, which is not needed
      on architectures that have memory-mapped PCI I/O space, however
      we now lack a pci_iomap() function.
      
      Fortunately, there is already a generic implementation for this
      case, so we just need to select GENERIC_PCI_IOMAP to make it all
      work.
      Signed-off-by: NArnd Bergmann <arnd@arndb.de>
      Fixes: 09a57239 ("arm64: Use include/asm-generic/io.h")
      cb61f676
  17. 10 11月, 2014 1 次提交
  18. 07 11月, 2014 1 次提交
    • S
      arm64: xchg: Implement cmpxchg_double · 5284e1b4
      Steve Capper 提交于
      The arm64 architecture has the ability to exclusively load and store
      a pair of registers from an address (ldxp/stxp). Also the SLUB can take
      advantage of a cmpxchg_double implementation to avoid taking some
      locks.
      
      This patch provides an implementation of cmpxchg_double for 64-bit
      pairs, and activates the logic required for the SLUB to use these
      functions (HAVE_ALIGNED_STRUCT_PAGE and HAVE_CMPXCHG_DOUBLE).
      
      Also definitions of this_cpu_cmpxchg_8 and this_cpu_cmpxchg_double_8
      are wired up to cmpxchg_local and cmpxchg_double_local (rather than the
      stock implementations that perform non-atomic operations with
      interrupts disabled) as they are used by the SLUB.
      
      On a Juno platform running on only the A57s I get quite a noticeable
      performance improvement with 5 runs of hackbench on v3.17:
      
               Baseline | With Patch
       -----------------+-----------
       Mean    119.2312 | 106.1782
       StdDev    0.4919 |   0.4494
      
      (times taken to complete `./hackbench 100 process 1000', in seconds)
      Signed-off-by: NSteve Capper <steve.capper@linaro.org>
      Signed-off-by: NWill Deacon <will.deacon@arm.com>
      5284e1b4
  19. 05 11月, 2014 1 次提交
  20. 24 10月, 2014 1 次提交
  21. 21 10月, 2014 1 次提交
  22. 10 10月, 2014 3 次提交
  23. 03 10月, 2014 1 次提交
  24. 02 10月, 2014 1 次提交
  25. 01 10月, 2014 1 次提交
  26. 23 9月, 2014 1 次提交
    • C
      Revert "arm64: dmi: Add SMBIOS/DMI support" · 6f325eaa
      Catalin Marinas 提交于
      This reverts commit 668ebd10.
      
      ... because of lots of warnings during boot if Linux isn't started as an EFI
      application:
      
      WARNING: CPU: 4 PID: 1 at
      /work/Linux/linux-2.6-aarch64/drivers/firmware/dmi_scan.c:591 dmi_matches+0x10c/0x110()
      dmi check: not initialized yet.
      Modules linked in:
      CPU: 4 PID: 1 Comm: swapper/0 Not tainted 3.17.0-rc4+ #606
      Call trace:
      [<ffffffc000087fb0>] dump_backtrace+0x0/0x124
      [<ffffffc0000880e4>] show_stack+0x10/0x1c
      [<ffffffc0004d58f8>] dump_stack+0x74/0xb8
      [<ffffffc0000ab640>] warn_slowpath_common+0x8c/0xb4
      [<ffffffc0000ab6b4>] warn_slowpath_fmt+0x4c/0x58
      [<ffffffc0003f2d7c>] dmi_matches+0x108/0x110
      [<ffffffc0003f2da8>] dmi_check_system+0x24/0x68
      [<ffffffc0006974c4>] atkbd_init+0x10/0x34
      [<ffffffc0000814ac>] do_one_initcall+0x88/0x1a0
      [<ffffffc00067aab4>] kernel_init_freeable+0x148/0x1e8
      [<ffffffc0004d2c64>] kernel_init+0x10/0xd4
      Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
      6f325eaa
  27. 22 9月, 2014 1 次提交
    • Y
      arm64: dmi: Add SMBIOS/DMI support · 668ebd10
      Yi Li 提交于
      SMBIOS is important for server hardware vendors. It implements a spec for
      providing descriptive information about the platform. Things like serial
      numbers, physical layout of the ports, build configuration data, and the like.
      
      This has been tested by dmidecode and lshw tools.
      
      This patch adds the call to dmi_scan_machine() to arm64_enter_virtual_mode(),
      as that is the point where the EFI Configuration Tables are registered as
      being available. It needs to be in an early_initcall anyway as dmi_id_init(),
      which is an arch_initcall itself, depends on dmi_scan_machine() having been
      called already.
      Signed-off-by: NYi Li <yi.li@linaro.org>
      Signed-off-by: NArd Biesheuvel <ard.biesheuvel@linaro.org>
      Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
      668ebd10
  28. 08 9月, 2014 2 次提交
  29. 03 9月, 2014 1 次提交
  30. 09 8月, 2014 1 次提交