1. 19 6月, 2018 2 次提交
  2. 06 6月, 2018 4 次提交
    • T
      genirq/affinity: Defer affinity setting if irq chip is busy · 12f47073
      Thomas Gleixner 提交于
      The case that interrupt affinity setting fails with -EBUSY can be handled
      in the kernel completely by using the already available generic pending
      infrastructure.
      
      If a irq_chip::set_affinity() fails with -EBUSY, handle it like the
      interrupts for which irq_chip::set_affinity() can only be invoked from
      interrupt context. Copy the new affinity mask to irq_desc::pending_mask and
      set the affinity pending bit. The next raised interrupt for the affected
      irq will check the pending bit and try to set the new affinity from the
      handler. This avoids that -EBUSY is returned when an affinity change is
      requested from user space and the previous change has not been cleaned
      up. The new affinity will take effect when the next interrupt is raised
      from the device.
      
      Fixes: dccfe314 ("x86/vector: Simplify vector move cleanup")
      Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
      Tested-by: NSong Liu <songliubraving@fb.com>
      Cc: Joerg Roedel <jroedel@suse.de>
      Cc: Peter Zijlstra <peterz@infradead.org>
      Cc: Song Liu <liu.song.a23@gmail.com>
      Cc: Dmitry Safonov <0x7f454c46@gmail.com>
      Cc: stable@vger.kernel.org
      Cc: Mike Travis <mike.travis@hpe.com>
      Cc: Borislav Petkov <bp@alien8.de>
      Cc: Tariq Toukan <tariqt@mellanox.com>
      Link: https://lkml.kernel.org/r/20180604162224.819273597@linutronix.de
      12f47073
    • T
      genirq/migration: Avoid out of line call if pending is not set · d340ebd6
      Thomas Gleixner 提交于
      The upcoming fix for the -EBUSY return from affinity settings requires to
      use the irq_move_irq() functionality even on irq remapped interrupts. To
      avoid the out of line call, move the check for the pending bit into an
      inline helper.
      
      Preparatory change for the real fix. No functional change.
      
      Fixes: dccfe314 ("x86/vector: Simplify vector move cleanup")
      Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
      Cc: Joerg Roedel <jroedel@suse.de>
      Cc: Peter Zijlstra <peterz@infradead.org>
      Cc: Song Liu <liu.song.a23@gmail.com>
      Cc: Dmitry Safonov <0x7f454c46@gmail.com>
      Cc: stable@vger.kernel.org
      Cc: Mike Travis <mike.travis@hpe.com>
      Cc: Borislav Petkov <bp@alien8.de>
      Cc: Tariq Toukan <tariqt@mellanox.com>
      Cc: Dou Liyang <douly.fnst@cn.fujitsu.com>
      Link: https://lkml.kernel.org/r/20180604162224.471925894@linutronix.de
      d340ebd6
    • T
      genirq/generic_pending: Do not lose pending affinity update · a33a5d2d
      Thomas Gleixner 提交于
      The generic pending interrupt mechanism moves interrupts from the interrupt
      handler on the original target CPU to the new destination CPU. This is
      required for x86 and ia64 due to the way the interrupt delivery and
      acknowledge works if the interrupts are not remapped.
      
      However that update can fail for various reasons. Some of them are valid
      reasons to discard the pending update, but the case, when the previous move
      has not been fully cleaned up is not a legit reason to fail.
      
      Check the return value of irq_do_set_affinity() for -EBUSY, which indicates
      a pending cleanup, and rearm the pending move in the irq dexcriptor so it's
      tried again when the next interrupt arrives.
      
      Fixes: 996c591227d9 ("x86/irq: Plug vector cleanup race")
      Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
      Tested-by: NSong Liu <songliubraving@fb.com>
      Cc: Joerg Roedel <jroedel@suse.de>
      Cc: Peter Zijlstra <peterz@infradead.org>
      Cc: Song Liu <liu.song.a23@gmail.com>
      Cc: Dmitry Safonov <0x7f454c46@gmail.com>
      Cc: stable@vger.kernel.org
      Cc: Mike Travis <mike.travis@hpe.com>
      Cc: Borislav Petkov <bp@alien8.de>
      Cc: Tariq Toukan <tariqt@mellanox.com>
      Link: https://lkml.kernel.org/r/20180604162224.386544292@linutronix.de
      a33a5d2d
    • S
      ide: don't enable/disable interrupts in force threaded-IRQ mode · 47b82e88
      Sebastian Andrzej Siewior 提交于
      The interrupts are enabled/disabled so the interrupt handler can run
      with enabled interrupts while serving the interrupt and not lose other
      interrupts especially the timer tick.
      If the system runs with force-threaded interrupts then there is no need
      to enable the interrupts.
      Signed-off-by: NSebastian Andrzej Siewior <bigeasy@linutronix.de>
      Acked-by: NDavid S. Miller <davem@davemloft.net>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      47b82e88
  3. 16 5月, 2018 1 次提交
  4. 13 5月, 2018 1 次提交
    • M
      genirq/msi: Allow level-triggered MSIs to be exposed by MSI providers · 0be8153c
      Marc Zyngier 提交于
      So far, MSIs have been used to signal edge-triggered interrupts, as
      a write is a good model for an edge (you can't "unwrite" something).
      On the other hand, routing zillions of wires in an SoC because you
      need level interrupts is a bit extreme.
      
      People have come up with a variety of schemes to support this, which
      involves sending two messages: one to signal the interrupt, and one
      to clear it. Since the kernel cannot represent this, we've ended up
      with side-band mechanisms that are pretty awful.
      
      Instead, let's acknoledge the requirement, and ensure that, under the
      right circumstances, the irq_compose_msg and irq_write_msg can take
      as a parameter an array of two messages instead of a pointer to a
      single one. We also add some checking that the compose method only
      clobbers the second message if the MSI domain has been created with
      the MSI_FLAG_LEVEL_CAPABLE flags.
      Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>
      Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
      Cc: Rob Herring <robh@kernel.org>
      Cc: Jason Cooper <jason@lakedaemon.net>
      Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
      Cc: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
      Cc: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
      Cc: Miquel Raynal <miquel.raynal@bootlin.com>
      Link: https://lkml.kernel.org/r/20180508121438.11301-2-marc.zyngier@arm.com
      0be8153c
  5. 27 4月, 2018 1 次提交
  6. 06 4月, 2018 5 次提交
    • M
      genirq/affinity: Spread irq vectors among present CPUs as far as possible · d3056812
      Ming Lei 提交于
      Commit 84676c1f ("genirq/affinity: assign vectors to all possible CPUs")
      tried to spread the interrupts accross all possible CPUs to make sure that
      in case of phsyical hotplug (e.g. virtualization) the CPUs which get
      plugged in after the device was initialized are targeted by a hardware
      queue and the corresponding interrupt.
      
      This has a downside in cases where the ACPI tables claim that there are
      more possible CPUs than present CPUs and the number of interrupts to spread
      out is smaller than the number of possible CPUs. These bogus ACPI tables
      are unfortunately not uncommon.
      
      In such a case the vector spreading algorithm assigns interrupts to CPUs
      which can never be utilized and as a consequence these interrupts are
      unused instead of being mapped to present CPUs. As a result the performance
      of the device is suboptimal.
      
      To fix this spread the interrupt vectors in two stages:
      
       1) Spread as many interrupts as possible among the present CPUs
      
       2) Spread the remaining vectors among non present CPUs
      
      On a 8 core system, where CPU 0-3 are present and CPU 4-7 are not present,
      for a device with 4 queues the resulting interrupt affinity is:
      
        1) Before 84676c1f ("genirq/affinity: assign vectors to all possible CPUs")
      	irq 39, cpu list 0
      	irq 40, cpu list 1
      	irq 41, cpu list 2
      	irq 42, cpu list 3
      
        2) With 84676c1f ("genirq/affinity: assign vectors to all possible CPUs")
      	irq 39, cpu list 0-2
      	irq 40, cpu list 3-4,6
      	irq 41, cpu list 5
      	irq 42, cpu list 7
      
        3) With the refined vector spread applied:
      	irq 39, cpu list 0,4
      	irq 40, cpu list 1,6
      	irq 41, cpu list 2,5
      	irq 42, cpu list 3,7
      
      On a 8 core system, where all CPUs are present the resulting interrupt
      affinity for the 4 queues is:
      
      	irq 39, cpu list 0,1
      	irq 40, cpu list 2,3
      	irq 41, cpu list 4,5
      	irq 42, cpu list 6,7
      
      This is independent of the number of CPUs which are online at the point of
      initialization because in such a system the offline CPUs can be easily
      onlined afterwards, while in non-present CPUs need to be plugged physically
      or virtually which requires external interaction.
      
      The downside of this approach is that in case of physical hotplug the
      interrupt vector spreading might be suboptimal when CPUs 4-7 are physically
      plugged. Suboptimal from a NUMA point of view and due to the single target
      nature of interrupt affinities the later plugged CPUs might not be targeted
      by interrupts at all.
      
      Though, physical hotplug systems are not the common case while the broken
      ACPI table disease is wide spread. So it's preferred to have as many
      interrupts as possible utilized at the point where the device is
      initialized.
      
      Block multi-queue devices like NVME create a hardware queue per possible
      CPU, so the goal of commit 84676c1f to assign one interrupt vector per
      possible CPU is still achieved even with physical/virtual hotplug.
      
      [ tglx: Changed from online to present CPUs for the first spreading stage,
        	renamed variables for readability sake, added comments and massaged
        	changelog ]
      Reported-by: NLaurence Oberman <loberman@redhat.com>
      Signed-off-by: NMing Lei <ming.lei@redhat.com>
      Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
      Reviewed-by: NChristoph Hellwig <hch@lst.de>
      Cc: Jens Axboe <axboe@kernel.dk>
      Cc: linux-block@vger.kernel.org
      Cc: Christoph Hellwig <hch@infradead.org>
      Link: https://lkml.kernel.org/r/20180308105358.1506-5-ming.lei@redhat.com
      d3056812
    • M
      genirq/affinity: Allow irq spreading from a given starting point · 1a2d0914
      Ming Lei 提交于
      To support two stage irq vector spreading, it's required to add a starting
      point to the spreading function. No functional change, just preparatory
      work for the actual two stage change.
      
      [ tglx: Renamed variables, tidied up the code and massaged changelog ]
      Signed-off-by: NMing Lei <ming.lei@redhat.com>
      Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
      Reviewed-by: NChristoph Hellwig <hch@lst.de>
      Cc: Jens Axboe <axboe@kernel.dk>
      Cc: linux-block@vger.kernel.org
      Cc: Laurence Oberman <loberman@redhat.com>
      Cc: Christoph Hellwig <hch@infradead.org>
      Link: https://lkml.kernel.org/r/20180308105358.1506-4-ming.lei@redhat.com
      1a2d0914
    • M
      genirq/affinity: Move actual irq vector spreading into a helper function · b3e6aaa8
      Ming Lei 提交于
      No functional change, just prepare for converting to 2-stage irq vector
      spreading.
      Signed-off-by: NMing Lei <ming.lei@redhat.com>
      Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
      Reviewed-by: NChristoph Hellwig <hch@lst.de>
      Cc: Jens Axboe <axboe@kernel.dk>
      Cc: linux-block@vger.kernel.org
      Cc: Laurence Oberman <loberman@redhat.com>
      Cc: Christoph Hellwig <hch@infradead.org>
      Link: https://lkml.kernel.org/r/20180308105358.1506-3-ming.lei@redhat.com
      b3e6aaa8
    • M
      genirq/affinity: Rename *node_to_possible_cpumask as *node_to_cpumask · 47778f33
      Ming Lei 提交于
      The following patches will introduce two stage irq spreading for improving
      irq spread on all possible CPUs.
      
      No functional change.
      Signed-off-by: NMing Lei <ming.lei@redhat.com>
      Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
      Reviewed-by: NChristoph Hellwig <hch@lst.de>
      Cc: Jens Axboe <axboe@kernel.dk>
      Cc: linux-block@vger.kernel.org
      Cc: Laurence Oberman <loberman@redhat.com>
      Cc: Christoph Hellwig <hch@infradead.org>
      Link: https://lkml.kernel.org/r/20180308105358.1506-2-ming.lei@redhat.com
      47778f33
    • T
      genirq/affinity: Don't return with empty affinity masks on error · 0211e12d
      Thomas Gleixner 提交于
      When the allocation of node_to_possible_cpumask fails, then
      irq_create_affinity_masks() returns with a pointer to the empty affinity
      masks array, which will cause malfunction.
      
      Reorder the allocations so the masks array allocation comes last and every
      failure path returns NULL.
      
      Fixes: 9a0ef98e ("genirq/affinity: Assign vectors to all present CPUs")
      Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
      Cc: Christoph Hellwig <hch@infradead.org>
      Cc: Ming Lei <ming.lei@redhat.com>
      0211e12d
  7. 04 4月, 2018 1 次提交
  8. 20 3月, 2018 5 次提交
  9. 15 3月, 2018 1 次提交
    • P
      genirq: Add CONFIG_GENERIC_IRQ_MULTI_HANDLER · caacdbf4
      Palmer Dabbelt 提交于
      The arm multi irq handler registration mechanism has been copied into a
      handful of architectures, including arm64 and openrisc. RISC-V needs the
      same mechanism.
      
      Instead of adding yet another copy for RISC-V copy the arm implementation
      into the core code depending on a new Kconfig symbol:
      CONFIG_GENERIC_MULTI_IRQ_HANDLER.
      
      Subsequent patches will convert the various architectures.
      Signed-off-by: NPalmer Dabbelt <palmer@sifive.com>
      Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
      Cc: jonas@southpole.se
      Cc: catalin.marinas@arm.com
      Cc: Will Deacon <will.deacon@arm.com>
      Cc: linux@armlinux.org.uk
      Cc: stefan.kristiansson@saunalahti.fi
      Cc: openrisc@lists.librecores.org
      Cc: shorne@gmail.com
      Cc: linux-riscv@lists.infradead.org
      Cc: linux-arm-kernel@lists.infradead.org
      Link: https://lkml.kernel.org/r/20180307235731.22627-2-palmer@sifive.com
      caacdbf4
  10. 09 3月, 2018 3 次提交
  11. 01 3月, 2018 1 次提交
  12. 23 2月, 2018 1 次提交
    • T
      genirq/matrix: Handle CPU offlining proper · 651ca2c0
      Thomas Gleixner 提交于
      At CPU hotunplug the corresponding per cpu matrix allocator is shut down and
      the allocated interrupt bits are discarded under the assumption that all
      allocated bits have been either migrated away or shut down through the
      managed interrupts mechanism.
      
      This is not true because interrupts which are not started up might have a
      vector allocated on the outgoing CPU. When the interrupt is started up
      later or completely shutdown and freed then the allocated vector is handed
      back, triggering warnings or causing accounting issues which result in
      suspend failures and other issues.
      
      Change the CPU hotplug mechanism of the matrix allocator so that the
      remaining allocations at unplug time are preserved and global accounting at
      hotplug is correctly readjusted to take the dormant vectors into account.
      
      Fixes: 2f75d9e1 ("genirq: Implement bitmap matrix allocator")
      Reported-by: NYuriy Vostrikov <delamonpansie@gmail.com>
      Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
      Tested-by: NYuriy Vostrikov <delamonpansie@gmail.com>
      Cc: Peter Zijlstra <peterz@infradead.org>
      Cc: Randy Dunlap <rdunlap@infradead.org>
      Cc: stable@vger.kernel.org
      Link: https://lkml.kernel.org/r/20180222112316.849980972@linutronix.de
      651ca2c0
  13. 16 2月, 2018 2 次提交
  14. 07 2月, 2018 1 次提交
  15. 01 2月, 2018 1 次提交
    • T
      genirq: Make legacy autoprobing work again · 1beaeacd
      Thomas Gleixner 提交于
      Meelis reported the following warning on a quad P3 HP NetServer museum piece:
      
      WARNING: CPU: 3 PID: 258 at kernel/irq/chip.c:244 __irq_startup+0x80/0x100
      EIP: __irq_startup+0x80/0x100
      irq_startup+0x7e/0x170
      probe_irq_on+0x128/0x2b0
      parport_irq_probe.constprop.18+0x8d/0x1af [parport_pc]
      parport_pc_probe_port+0xf11/0x1260 [parport_pc]
      parport_pc_init+0x78a/0xf10 [parport_pc]
      parport_parse_param.constprop.16+0xf0/0xf0 [parport_pc]
      do_one_initcall+0x45/0x1e0
      
      This is caused by the rewrite of the irq activation/startup sequence which
      missed to convert a callsite in the irq legacy auto probing code.
      
      To fix this irq_activate_and_startup() needs to gain a return value so the
      pending logic can work proper.
      
      Fixes: c942cee4 ("genirq: Separate activation and startup")
      Reported-by: NMeelis Roos <mroos@linux.ee>
      Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
      Tested-by: NMeelis Roos <mroos@linux.ee>
      Cc: stable@vger.kernel.org
      Link: https://lkml.kernel.org/r/alpine.DEB.2.20.1801301935410.1797@nanos
      1beaeacd
  16. 24 1月, 2018 1 次提交
  17. 18 1月, 2018 1 次提交
    • T
      irq/matrix: Spread interrupts on allocation · a0c9259d
      Thomas Gleixner 提交于
      Keith reported an issue with vector space exhaustion on a server machine
      which is caused by the i40e driver allocating 168 MSI interrupts when the
      driver is initialized, even when most of these interrupts are not used at
      all.
      
      The x86 vector allocation code tries to avoid the immediate allocation with
      the reservation mode, but the card uses MSI and does not support MSI entry
      masking, which prevents reservation mode and requires immediate vector
      allocation.
      
      The matrix allocator is a bit naive and prefers the first CPU in the
      cpumask which describes the possible target CPUs for an allocation. That
      results in allocating all 168 vectors on CPU0 which later causes vector
      space exhaustion when the NVMe driver tries to allocate managed interrupts
      on each CPU for the per CPU queues.
      
      Avoid this by finding the CPU which has the lowest vector allocation count
      to spread out the non managed interrupt accross the possible target CPUs.
      
      Fixes: 2f75d9e1 ("genirq: Implement bitmap matrix allocator")
      Reported-by: NKeith Busch <keith.busch@intel.com>
      Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
      Tested-by: NKeith Busch <keith.busch@intel.com>
      Link: https://lkml.kernel.org/r/alpine.DEB.2.20.1801171557330.1777@nanos
      a0c9259d
  18. 13 1月, 2018 1 次提交
  19. 05 1月, 2018 1 次提交
    • S
      irq debug: do not use print_symbol() · 3b14f08d
      Sergey Senozhatsky 提交于
      print_symbol() is a very old API that has been obsoleted by %pS format
      specifier in a normal printk() call.
      
      Replace print_symbol() with a direct printk("%pS") call and avoid
      using continuous lines.
      
      Link: http://lkml.kernel.org/r/20171212073453.21455-1-sergey.senozhatsky@gmail.com
      To: Andrew Morton <akpm@linux-foundation.org>
      To: Russell King <linux@armlinux.org.uk>
      To: Catalin Marinas <catalin.marinas@arm.com>
      To: Mark Salter <msalter@redhat.com>
      To: Tony Luck <tony.luck@intel.com>
      To: David Howells <dhowells@redhat.com>
      To: Yoshinori Sato <ysato@users.sourceforge.jp>
      To: Guan Xuetao <gxt@mprc.pku.edu.cn>
      To: Borislav Petkov <bp@alien8.de>
      To: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
      To: Thomas Gleixner <tglx@linutronix.de>
      To: Peter Zijlstra <peterz@infradead.org>
      To: Vineet Gupta <vgupta@synopsys.com>
      To: Fengguang Wu <fengguang.wu@intel.com>
      To: David Laight <David.Laight@ACULAB.COM>
      Cc: Steven Rostedt <rostedt@goodmis.org>
      Cc: Petr Mladek <pmladek@suse.com>
      Cc: LKML <linux-kernel@vger.kernel.org>
      Cc: linux-arm-kernel@lists.infradead.org
      Cc: linux-c6x-dev@linux-c6x.org
      Cc: linux-ia64@vger.kernel.org
      Cc: linux-am33-list@redhat.com
      Cc: linux-sh@vger.kernel.org
      Cc: linux-edac@vger.kernel.org
      Cc: x86@kernel.org
      Cc: linux-snps-arc@lists.infradead.org
      Signed-off-by: NSergey Senozhatsky <sergey.senozhatsky@gmail.com>
      [pmladek@suse.com: updated commit message]
      Signed-off-by: NPetr Mladek <pmladek@suse.com>
      3b14f08d
  20. 30 12月, 2017 4 次提交
    • T
      genirq/msi, x86/vector: Prevent reservation mode for non maskable MSI · bc976233
      Thomas Gleixner 提交于
      The new reservation mode for interrupts assigns a dummy vector when the
      interrupt is allocated and assigns a real vector when the interrupt is
      requested. The reservation mode prevents vector pressure when devices with
      a large amount of queues/interrupts are initialized, but only a minimal
      subset of those queues/interrupts is actually used.
      
      This mode has an issue with MSI interrupts which cannot be masked. If the
      driver is not careful or the hardware emits an interrupt before the device
      irq is requestd by the driver then the interrupt ends up on the dummy
      vector as a spurious interrupt which can cause malfunction of the device or
      in the worst case a lockup of the machine.
      
      Change the logic for the reservation mode so that the early activation of
      MSI interrupts checks whether:
      
       - the device is a PCI/MSI device
       - the reservation mode of the underlying irqdomain is activated
       - PCI/MSI masking is globally enabled
       - the PCI/MSI device uses either MSI-X, which supports masking, or
         MSI with the maskbit supported.
      
      If one of those conditions is false, then clear the reservation mode flag
      in the irq data of the interrupt and invoke irq_domain_activate_irq() with
      the reserve argument cleared. In the x86 vector code, clear the can_reserve
      flag in the vector allocation data so a subsequent free_irq() won't create
      the same situation again. The interrupt stays assigned to a real vector
      until pci_disable_msi() is invoked and all allocations are undone.
      
      Fixes: 4900be83 ("x86/vector/msi: Switch to global reservation mode")
      Reported-by: NAlexandru Chirvasitu <achirvasub@gmail.com>
      Reported-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com>
      Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
      Tested-by: NAlexandru Chirvasitu <achirvasub@gmail.com>
      Tested-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com>
      Cc: Dou Liyang <douly.fnst@cn.fujitsu.com>
      Cc: Pavel Machek <pavel@ucw.cz>
      Cc: Maciej W. Rozycki <macro@linux-mips.org>
      Cc: Mikael Pettersson <mikpelinux@gmail.com>
      Cc: Josh Poulson <jopoulso@microsoft.com>
      Cc: Mihai Costache <v-micos@microsoft.com>
      Cc: Stephen Hemminger <sthemmin@microsoft.com>
      Cc: Marc Zyngier <marc.zyngier@arm.com>
      Cc: linux-pci@vger.kernel.org
      Cc: Haiyang Zhang <haiyangz@microsoft.com>
      Cc: Dexuan Cui <decui@microsoft.com>
      Cc: Simon Xiao <sixiao@microsoft.com>
      Cc: Saeed Mahameed <saeedm@mellanox.com>
      Cc: Jork Loeser <Jork.Loeser@microsoft.com>
      Cc: Bjorn Helgaas <bhelgaas@google.com>
      Cc: devel@linuxdriverproject.org
      Cc: KY Srinivasan <kys@microsoft.com>
      Cc: Alan Cox <alan@linux.intel.com>
      Cc: Sakari Ailus <sakari.ailus@intel.com>,
      Cc: linux-media@vger.kernel.org
      Link: https://lkml.kernel.org/r/alpine.DEB.2.20.1712291406420.1899@nanos
      Link: https://lkml.kernel.org/r/alpine.DEB.2.20.1712291409460.1899@nanos
      bc976233
    • T
      genirq/irqdomain: Rename early argument of irq_domain_activate_irq() · 702cb0a0
      Thomas Gleixner 提交于
      The 'early' argument of irq_domain_activate_irq() is actually used to
      denote reservation mode. To avoid confusion, rename it before abuse
      happens.
      
      No functional change.
      
      Fixes: 72491643 ("genirq/irqdomain: Update irq_domain_ops.activate() signature")
      Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
      Cc: Alexandru Chirvasitu <achirvasub@gmail.com>
      Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
      Cc: Dou Liyang <douly.fnst@cn.fujitsu.com>
      Cc: Pavel Machek <pavel@ucw.cz>
      Cc: Maciej W. Rozycki <macro@linux-mips.org>
      Cc: Mikael Pettersson <mikpelinux@gmail.com>
      Cc: Josh Poulson <jopoulso@microsoft.com>
      Cc: Mihai Costache <v-micos@microsoft.com>
      Cc: Stephen Hemminger <sthemmin@microsoft.com>
      Cc: Marc Zyngier <marc.zyngier@arm.com>
      Cc: linux-pci@vger.kernel.org
      Cc: Haiyang Zhang <haiyangz@microsoft.com>
      Cc: Dexuan Cui <decui@microsoft.com>
      Cc: Simon Xiao <sixiao@microsoft.com>
      Cc: Saeed Mahameed <saeedm@mellanox.com>
      Cc: Jork Loeser <Jork.Loeser@microsoft.com>
      Cc: Bjorn Helgaas <bhelgaas@google.com>
      Cc: devel@linuxdriverproject.org
      Cc: KY Srinivasan <kys@microsoft.com>
      Cc: Alan Cox <alan@linux.intel.com>
      Cc: Sakari Ailus <sakari.ailus@intel.com>,
      Cc: linux-media@vger.kernel.org
      702cb0a0
    • T
      genirq: Introduce IRQD_CAN_RESERVE flag · 69790ba9
      Thomas Gleixner 提交于
      Add a new flag to mark interrupts which can use reservation mode. This is
      going to be used in subsequent patches to disable reservation mode for a
      certain class of MSI devices.
      Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
      Tested-by: NAlexandru Chirvasitu <achirvasub@gmail.com>
      Tested-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com>
      Cc: Dou Liyang <douly.fnst@cn.fujitsu.com>
      Cc: Pavel Machek <pavel@ucw.cz>
      Cc: Maciej W. Rozycki <macro@linux-mips.org>
      Cc: Mikael Pettersson <mikpelinux@gmail.com>
      Cc: Josh Poulson <jopoulso@microsoft.com>
      Cc: Mihai Costache <v-micos@microsoft.com>
      Cc: Stephen Hemminger <sthemmin@microsoft.com>
      Cc: Marc Zyngier <marc.zyngier@arm.com>
      Cc: linux-pci@vger.kernel.org
      Cc: Haiyang Zhang <haiyangz@microsoft.com>
      Cc: Dexuan Cui <decui@microsoft.com>
      Cc: Simon Xiao <sixiao@microsoft.com>
      Cc: Saeed Mahameed <saeedm@mellanox.com>
      Cc: Jork Loeser <Jork.Loeser@microsoft.com>
      Cc: Bjorn Helgaas <bhelgaas@google.com>
      Cc: devel@linuxdriverproject.org
      Cc: KY Srinivasan <kys@microsoft.com>
      Cc: Alan Cox <alan@linux.intel.com>
      Cc: Sakari Ailus <sakari.ailus@intel.com>,
      Cc: linux-media@vger.kernel.org
      69790ba9
    • T
      genirq/msi: Handle reactivation only on success · da5dd9e8
      Thomas Gleixner 提交于
      When analyzing the fallout of the x86 vector allocation rework it turned
      out that the error handling in msi_domain_alloc_irqs() is broken.
      
      If MSI_FLAG_MUST_REACTIVATE is set for a MSI domain then it clears the
      activation flag for a successfully initialized msi descriptor. If a
      subsequent initialization fails then the error handling code path does not
      deactivate the interrupt because the activation flag got cleared.
      
      Move the clearing of the activation flag outside of the initialization loop
      so that an eventual failure can be cleaned up correctly.
      
      Fixes: 22d0b12f ("genirq/irqdomain: Add force reactivation flag to irq domains")
      Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
      Tested-by: NAlexandru Chirvasitu <achirvasub@gmail.com>
      Tested-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com>
      Cc: Dou Liyang <douly.fnst@cn.fujitsu.com>
      Cc: Pavel Machek <pavel@ucw.cz>
      Cc: Maciej W. Rozycki <macro@linux-mips.org>
      Cc: Mikael Pettersson <mikpelinux@gmail.com>
      Cc: Josh Poulson <jopoulso@microsoft.com>
      Cc: Mihai Costache <v-micos@microsoft.com>
      Cc: Stephen Hemminger <sthemmin@microsoft.com>
      Cc: Marc Zyngier <marc.zyngier@arm.com>
      Cc: linux-pci@vger.kernel.org
      Cc: Haiyang Zhang <haiyangz@microsoft.com>
      Cc: Dexuan Cui <decui@microsoft.com>
      Cc: Simon Xiao <sixiao@microsoft.com>
      Cc: Saeed Mahameed <saeedm@mellanox.com>
      Cc: Jork Loeser <Jork.Loeser@microsoft.com>
      Cc: Bjorn Helgaas <bhelgaas@google.com>
      Cc: devel@linuxdriverproject.org
      Cc: KY Srinivasan <kys@microsoft.com>
      Cc: Alan Cox <alan@linux.intel.com>
      Cc: Sakari Ailus <sakari.ailus@intel.com>,
      Cc: linux-media@vger.kernel.org
      
      da5dd9e8
  21. 28 12月, 2017 2 次提交