Fix the return value of exynos_dp_get_pll_lock_status to
reflect what it actually returns.
Signed-off-by: NSean Paul <seanpaul@chromium.org>
Reviewed-by: NOlof Johansson <olofj@chromium.org>
Acked-by: NJingoo Han <jg1.han@samsung.com>
Signed-off-by: NFlorian Tobias Schandinat <FlorianSchandinat@gmx.de>

This patch adds adjustement for voltage swing and pre-emphasis during
Link Training procedure. According to the DP specification, unless all
the LANEx_CR_DONE bits are set, the transmitter must read
the ADJUST_REQUEST_LANEx_x, increase the voltage swing according to
the request, and update the TRAINING_LANEx_SET bytes to match the new
voltage swing setting.

Refer to the DP specification v1.1a, Section 3.5.1.3 Link Training.
Signed-off-by: NJingoo Han <jg1.han@samsung.com>
Signed-off-by: NFlorian Tobias Schandinat <FlorianSchandinat@gmx.de>

Some functions are declared twice in header file; thus, these
declarations are unnecessary.
Signed-off-by: NJingoo Han <jg1.han@samsung.com>
Signed-off-by: NFlorian Tobias Schandinat <FlorianSchandinat@gmx.de>

The sw reset should be called prioir to enabling sw defined function,
according to datasheet.
Signed-off-by: NJingoo Han <jg1.han@samsung.com>
Signed-off-by: NFlorian Tobias Schandinat <FlorianSchandinat@gmx.de>

The devm_ functions allocate memory that is released when a driver
detaches. This makes the code smaller and a bit simpler.
Signed-off-by: NJingoo Han <jg1.han@samsung.com>
Signed-off-by: NFlorian Tobias Schandinat <FlorianSchandinat@gmx.de>

This patch adds analog and pll control setting. This control setting
is used for DP TX PHY block to set the values as below. It is beneficial
to improve analog characteristics.
 - TX terminal registor is 50 Ohm.
 - Reference clock of PHY is 24 MHz.
 - Power source for TX digital logic is 1.0625 V.
 - Power source for internal clock driver is 1.0625 V.
 - PLL VCO range setting is 600 uA.
 - Power down ring osc is turned off.
 - AUX terminal resistor is 50 Ohm.
 - AUX channel current is 8 mA and multiplied by 2.
 - TX channel output amplitude is 400 mV.
Signed-off-by: NJingoo Han <jg1.han@samsung.com>
Signed-off-by: NFlorian Tobias Schandinat <FlorianSchandinat@gmx.de>

Samsung EXYNOS SoC such Exynos5 has DP controller and embedded DP
panel can be used. This patch supports DP driver based on Samsung
EXYNOS SoC chip.
Signed-off-by: NJingoo Han <jg1.han@samsung.com>
Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: NFlorian Tobias Schandinat <FlorianSchandinat@gmx.de>