1. 25 10月, 2006 8 次提交
  2. 24 10月, 2006 3 次提交
  3. 23 10月, 2006 3 次提交
  4. 18 10月, 2006 2 次提交
    • M
      [POWERPC] More bootwrapper reorganization · c888554b
      Mark A. Greer 提交于
      More reorganization of the bootwrapper:
      - Add dtb section to zImage
      - ft_init now called by platform_init
      - Pack a flat dt before calling kernel
      - Remove size parameter from free
      - printf only calls console_ops.write it its not NULL
      - Some cleanup
      Signed-off-by: NMark A. Greer <mgreer@mvista.com>
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      c888554b
    • P
      [POWERPC] Make sure interrupt enable gets restored properly · b0a779de
      Paul Mackerras 提交于
      The lazy IRQ disable patch missed a couple of places where the
      interrupt enable flags need to be restored correctly.  First, we
      weren't restoring the paca->hard_enabled flag on interrupt exit.
      Instead of saving it on entry, we compute it from the MSR_EE bit
      in the MSR we are restoring at exit.  Secondly, the MMU hash miss
      code was clearing both paca->soft_enabled and paca->hard_enabled
      but not restoring them in the case where hash_page was able to
      resolve the miss from the Linux page tables.
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      b0a779de
  5. 16 10月, 2006 17 次提交
  6. 14 10月, 2006 2 次提交
    • K
      ACPI: SCI interrupt source override · 281ea49b
      Kimball Murray 提交于
      The Linux group at Stratus Technologies has come across an issue with SCI
      routing under ACPI.  We were bitten by this when we made an x86_64 platform
      whose BIOS provides an Interrupt Source Override for the SCI itself.
      Apparently the override has no effect for the System Control Interrupt, and
      this appears to be because of the way the SCI is setup in the ACPI code.
      It does not handle the case where busirq != gsi.
      
      The code that sets up the SCI routing assumes that bus irq == global irq.
      So there is simply no provision for telling it otherwise.  The attached
      patch provides this mechanism.
      
      This patch provided by David Bulkow, was tested on an i386 platform, which
      does not use the SCI override, and also on an x86_64 platform which does
      use an override.
      Signed-off-by: NDavid Bulkow <david.bulkow@stratus.com>
      Cc: Andi Kleen <ak@muc.de>
      Signed-off-by: NAndrew Morton <akpm@osdl.org>
      Signed-off-by: NLen Brown <len.brown@intel.com>
      281ea49b
    • V
      ACPI: Processor native C-states using MWAIT · 991528d7
      Venkatesh Pallipadi 提交于
      Intel processors starting with the Core Duo support
      support processor native C-state using the MWAIT instruction.
      Refer: Intel Architecture Software Developer's Manual
      http://www.intel.com/design/Pentium4/manuals/253668.htm
      
      Platform firmware exports the support for Native C-state to OS using
      ACPI _PDC and _CST methods.
      Refer: Intel Processor Vendor-Specific ACPI: Interface Specification
      http://www.intel.com/technology/iapc/acpi/downloads/302223.htm
      
      With Processor Native C-state, we use 'MWAIT' instruction on the processor
      to enter different C-states (C1, C2, C3).  We won't use the special IO
      ports to enter C-state and no SMM mode etc required to enter C-state.
      Overall this will mean better C-state support.
      
      One major advantage of using MWAIT for all C-states is, with this and
      "treat interrupt as break event" feature of MWAIT, we can now get accurate
      timing for the time spent in C1, C2, ..  states.
      Signed-off-by: NVenkatesh Pallipadi <venkatesh.pallipadi@intel.com>
      Signed-off-by: NAndrew Morton <akpm@osdl.org>
      Signed-off-by: NLen Brown <len.brown@intel.com>
      991528d7
  7. 13 10月, 2006 5 次提交