This patch adds sleep mode pin configuration using pin control hog
mechanism to configure states of GPIO pins in sleep mode. This is
required to reduce leakage current in sleep mode and prevent glitching
of components on the board.
Signed-off-by: NTomasz Figa <t.figa@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

This patch adds a convenient macro which constructs an Exynos pinctrl
pinconf node containing properties needed to configure sleep state of
given pin with given parameters. It will be used by further patch which
adds a large number of sleep states for pins that need such
configuration on certain boards.
Signed-off-by: NTomasz Figa <t.figa@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

In MAX77686 PMIC two regulators dedicated for eMMC memory can be
controlled both by I2C interface and a GPIO pin, with the resulting
regulator state being a logical OR of both. Since the GPIO control is
used both by the kernel and the lowest level bootloader at reset, the
regulator should be disabled by I2C control to allow it to be turned off
by GPIO control.

This patch removes regulator-always-on properties from both regulators
and, while at it, also unsupported regulator-mem-off.
Signed-off-by: NTomasz Figa <t.figa@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

MMC capability for HS200 is parsed in mmc/core/host.c as
dts string "mmc-hs200-1_8v".

This patch corrects the dts string for Exynos5420 based peach-pit
and Exynos5800 based peach-pi boards.
Signed-off-by: NNaveen Krishna Chatradhi <ch.naveen@samsung.com>
Signed-off-by: NVivek Gautam <gautam.vivek@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

commit 546b117fdf17 ("rtc: s3c: add support for RTC of Exynos3250 SoC")
added an "rtc_src" DT property for the Samsung's S3C Real Time Clock
controller that specifies the 32.768 kHz clock that uses the RTC as
its source clock. In the case of the Exynos5250 based Snow board, the
Maxim 77686 32kHz AP clock is used as the source clock.
Signed-off-by: NJavier Martinez Canillas <javier.martinez@collabora.co.uk>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

commit 546b117fdf17 ("rtc: s3c: add support for RTC of Exynos3250 SoC")
added an "rtc_src" DT property for the Samsung's S3C Real Time Clock
controller that specifies the 32.768 kHz clock that uses the RTC as
its source clock. In the case of the Peach Pit and Pi machines, the
Maxim 77802 32kHz AP clock is used as the source clock.
Signed-off-by: NJavier Martinez Canillas <javier.martinez@collabora.co.uk>
Reviewed-by: NDoug Anderson <dianders@chromium.org>
Reviewed-by: NChanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

The PWM block is required for system clock source so it must be always
enabled. This patch fixes boot issues on SMDK6410 which did not have
the node enabled explicitly for other purposes.

Fixes: eeb93d02 ("clocksource: of: Respect device tree node status")
Signed-off-by: NTomasz Figa <tomasz.figa@gmail.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Adds initial support for the HP Chromebook 11.

Cc: Vincent Palatin <vpalatin@chromium.org>
Cc: Doug Anderson <dianders@chromium.org>
Cc: Stephan van Schaik <stephan@synkhronix.com>
Signed-off-by: NAndreas Faerber <afaerber@suse.de>
Reviewed-by: NTomasz Figa <t.figa@samsung.com>
Reviewed-by: NDoug Anderson <dianders@chromium.org>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

There's no need for a simple-bus, place the smsc,usb3503a directly into
the root node. That's what we're going to do on exynos5250-spring.
Reported-by: NTomasz Figa <t.figa@samsung.com>
Reviewed-by: NTomasz Figa <t.figa@samsung.com>
Signed-off-by: NAndreas Faerber <afaerber@suse.de>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

The GPIO flag 2 has no constant assigned, so this was probably
active-low.
Reviewed-by: NTomasz Figa <t.figa@samsung.com>
Signed-off-by: NAndreas Faerber <afaerber@suse.de>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Use the new style of referencing inherited nodes, use symbolic names,
tidy indentation and reorder includes.

Goal is the alignment of all exynos5250 based device trees for
comparison.
Signed-off-by: NAndreas Faerber <afaerber@suse.de>
Reviewed-by: NTomasz Figa <t.figa@samsung.com>
[kgene.kim@samsung.com: rebased]
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Use the new style for referencing inherited nodes and use symbolic
names. Goal is the alignment of all exynos5250 based device trees
for comparison.
Signed-off-by: NAndreas Faerber <afaerber@suse.de>
Reviewed-by: NTomasz Figa <t.figa@samsung.com>
[kgene.kim@samsung.com: rebased and squashed]
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

exynos5250-cros-common.dtsi had an empty /chosen node.
Fill in exemplary boot arguments.
Reviewed-by: NTomasz Figa <t.figa@samsung.com>
Signed-off-by: NAndreas Faerber <afaerber@suse.de>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Use the new style of referencing inherited nodes and use symbolic
names. Reorder one pinctrl node in GPIO order.
Goal is the alignment of all exynos5250 based device trees for
comparison.
Suggested-by: NDoug Anderson <dianders@chromium.org>
Reviewed-by: NDoug Anderson <dianders@chromium.org>
Signed-off-by: NAndreas Faerber <afaerber@suse.de>
Reviewed-by: NTomasz Figa <t.figa@samsung.com>
[kgene.kim@samsung.com: rebased and squashed]
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Allows them to be extended by reference.
Reviewed-by: NDoug Anderson <dianders@chromium.org>
Signed-off-by: NAndreas Faerber <afaerber@suse.de>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Explicitly set the dr_mode for the second dwc3 controller on the
Arndale Octa board to host mode. This is required to ensure the
controller is initialized in the right mode if the kernel is build
with USB gadget support.
Reported-By: NAndreas Faerber <afaerber@suse.de>
Signed-off-by: NSjoerd Simons <sjoerd.simons@collabora.co.uk>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

In case the optional dr_mode property isn't set in the dwc3 nodes the
the controller will go into OTG mode if both USB host and USB gadget
functionality are enabled in the kernel configuration. Unfortunately
this results in USB not working on exynos5420-peach-pit and
exynos5800-peach-pi with such a kernel configuration unless manually
change the mode. To resolve that explicitly configure the dual role
mode as host.
Signed-off-by: NSjoerd Simons <sjoerd.simons@collabora.co.uk>
Reviewed-by: NAndreas Faerber <afaerber@suse.de>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

CM-QS600 is a APQ8064 based computer on module.
The details are available at
http://compulab.co.il/products/computer-on-modules/cm-qs600/Signed-off-by: NMike Rapoport <mike.rapoport@gmail.com>
Acked-by: NIgor Grinberg <grinberg@compulab.co.il>
Signed-off-by: NKumar Gala <galak@codeaurora.org>

This DTS has support for the Sony Xperia Z1 phone (codenamed Honami).
This first version of the DTS supports just a serial console.
Signed-off-by: NTim Bird <tim.bird@sonymobile.com>
Tested-by: NKevin Hilman <khilman@linaro.org>
Signed-off-by: NKumar Gala <galak@codeaurora.org>

Add SATA PHY and SATA AHCI controller nodes to device tree to enable
generic ahci support on the IPQ8064/AP148 board.
Signed-off-by: NKumar Gala <galak@codeaurora.org>

Fix wrong compatible string of Exynos3250 RTC (Real-Time Clock) dt node.
The RTC of Exynos3250 must need additional source clock (XrtcXTI).
Signed-off-by: NChanwoo Choi <cw00.choi@samsung.com>
Acked-by: NKyungmin Park <kyungmin.park@samsung.com>
Cc: Alessandro Zummo <a.zummo@towertech.it>
Cc: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>

I added smc91x support but turns out we currently do not set the
smc91x timings in gpmc.c but rely on the bootloader timings. This
produces the following error unless the smc91x GPMC timings are
initialized by the bootloader:

Unhandled fault: external abort on non-linefetch (0x1008) at 0xd080630e
...
[<c04067fc>] (smc_drv_probe) from [<c038e9c4>] (platform_drv_probe+0x2c/0x5c)
[<c038e9c4>] (platform_drv_probe) from [<c038d450>] (driver_probe_device+0x104/0x22c)
[<c038d450>] (driver_probe_device) from [<c038d60c>] (__driver_attach+0x94/0x98)
[<c038d60c>] (__driver_attach) from [<c038bc3c>] (bus_for_each_dev+0x54/0x88)
[<c038bc3c>] (bus_for_each_dev) from [<c038cc3c>] (bus_add_driver+0xd8/0x1d8)
[<c038cc3c>] (bus_add_driver) from [<c038dd74>] (driver_register+0x78/0xf4)
[<c038dd74>] (driver_register) from [<c0008924>] (do_one_initcall+0x80/0x1c0)
[<c0008924>] (do_one_initcall) from [<c0852d9c>] (kernel_init_freeable+0x1b8/0x28c)
[<c0852d9c>] (kernel_init_freeable) from [<c05ce86c>] (kernel_init+0x8/0xec)
[<c05ce86c>] (kernel_init) from [<c000e728>] (ret_from_fork+0x14/0x2c)

Let's fix the issue by disabling the smc91x module for now until we
have sorted out the issues in gpmc.c.
Reported-by: NKevin Hilman <khilman@linaro.org>
Tested-by: NKevin Hilman <khilman@linaro.org>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Regulators for MMC2 (SD card) are PVDD_TFLASH_2V8 (LDO19) for vmmc
and PVDD_APIO_MMCOFF_2V8 (LDO13) for vqmmc.  Currently the device
tree entry for MMC2 uses PVDD_PRE_1V8 (LDO10) for vmmc and vqmmc is
not specified.  Fix it.

Without this patch:
- "mmc: dw_mmc: use mmc_regulator_get_supply to handle regulators"
  patch causes a SD card detection to fail
- "mmc: dw_mmc: Support voltage changes" patch causes a boot hang

This patch fixes both above problems.
Suggested-by: NDoug Anderson <dianders@google.com>
Cc: Yuvaraj Kumar C D <yuvaraj.cd@samsung.com>
Cc: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: NBartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Acked-by: NKyungmin Park <kyungmin.park@samsung.com>
Fixes: 01730558 ("mmc: dw_mmc: Support voltage changes")
Acked-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Reviewed-by: NGuenter Roeck <linux@roeck-us.net>
Signed-off-by: NCarlo Caione <carlo@caione.org>

The K2L MDIO io space has different start address.
Hence, fix it to be 0x26200f00 according to TRM.
Signed-off-by: NGrygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>

The K2E MDIO io space has different start address.
Hence, fix it to be 0x24200f00 according to TRM.
Signed-off-by: NGrygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>

Keystone supports dma-coherent on USB master and also needs
dma-ranges to specify the hardware alias memory range in which DMA
can be operational.
Such configuration applied for USB0 devices, but It's missed for
USB1 device which is present only in K2E SoC - hence apply it.
Signed-off-by: NGrygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>

The IO range size is set incorrectly for USB PHY0 deivice
it should be 24 instead of 32. Otherwise, It causes
USB PHY1 probing failure.
Signed-off-by: NGrygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>

This patch enables the Ethernet port on the Marvell Berlin2Q DMP board.
Signed-off-by: NAntoine Tenart <antoine.tenart@free-electrons.com>
Acked-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

This patch adds the Ethernet node, enabling the network unit on Berlin
BG2Q SoCs.
Signed-off-by: NAntoine Tenart <antoine.tenart@free-electrons.com>
Acked-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

Add the clock tree description for the PXA27x based boards.
Signed-off-by: NRobert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

There are 2 MACIDs stored in the control module of the am33xx. These are
read by the cpsw driver if no valid MACID was found in the devicetree.
Signed-off-by: NMarkus Pargmann <mpa@pengutronix.de>
Reviewed-by: NWolfram Sang <wsa@the-dreams.de>
Acked-by: NTony Lindgren <tony@atomide.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

Signed-off-by: NMarkus Pargmann <mpa@pengutronix.de>
Reviewed-by: NWolfram Sang <wsa@the-dreams.de>
Acked-by: NTony Lindgren <tony@atomide.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

Now that we have a compatible of its own for the mbus clock, switch to it.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: NHans de Goede <hdegoede@redhat.com>

Apparently most of the newly added nodes had the same problem,
so instead of reverting the individual patches, this undoes
the effect of the merge and backs out all of them at once.
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

This reverts commit 610bd872.

"ARM: dts: hix5hd2: add wdg node" causes a build breakage due to
an undefined constatns:

Error: arch/arm/boot/dts/hisi-x5hd2.dtsi:374.22-23 syntax error

(Don't you just looove the dtc error messages? They are so informative!)
Signed-off-by: NOlof Johansson <olof@lixom.net>

Add dt for rk3288 i2s controller, since i2s clock pins and data pins
default to be GPIO, this patch also add pinctrl to mux them.

Tested on RK3288 board.
Signed-off-by: NJianqun Xu <jay.xu@rock-chips.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

... for V2M-P1 motherboard CLCD (limited to 640x480 16bpp and using
dedicated video RAM bank) and for V2P-CA9 (up to 1024x768 16bpp).
Signed-off-by: NPawel Moll <pawel.moll@arm.com>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

Signed-off-by: NFlorian Meier <florian.meier@koalo.de>
[Tweaked slightly to disable by default -- broonie]
Signed-off-by: NMark Brown <broonie@linaro.org>
[swarren, removed duplicate i2s node]
Signed-off-by: NStephen Warren <swarren@wwwdotorg.org>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

The Meson6 SoC is produced by Amlogic inc. and it is based on 2 Cortex
A9 and an ARM Mali-400 GPU.
This patch adds two basic DTSI for the preliminary support of Meson and
Meson6 SoCs. Another DTS is also added for supporting the atv1200 board,
produced by Geniatech inc.
Signed-off-by: NCarlo Caione <carlo@caione.org>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>