The GPIO block for ls2080a platform has little endian registers,
the GPIO driver needs this property to read/write registers by
right interface.
Signed-off-by: NLiu Gang <Gang.Liu@freescale.com>
Signed-off-by: NLi Yang <leoli@freescale.com>
Signed-off-by: NKevin Hilman <khilman@linaro.org>

Add the "little-endian" property to fix the issue that eSDHC
is not working and dumping out "mmc0: Controller never released
inhibit bit(s)." error messages constantly.

Fixes: 5461597f ("dts/ls2080a: Update DTSI to add support of various peripherals")
Signed-off-by: NYangbo Lu <yangbo.lu@freescale.com>
Signed-off-by: NLi Yang <leoli@freescale.com>
Signed-off-by: NKevin Hilman <khilman@linaro.org>

After discussing on the mailing list it turns out that
accessing the flash memory from the kernel can disrupt CPU
sleep states and CPU hotplugging, so let's disable this
DT node by default. Setups that want to access the flash
can modify this entry to enable the flash again.

Quoting Sudeep Holla: "the firmware assumes the flash is
always in read mode while Linux leaves NOR flash in
"read id" mode after initialization."
Reported-by: NSudeep Holla <sudeep.holla@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Sudeep Holla <sudeep.holla@arm.com>
Cc: Liviu Dudau <Liviu.Dudau@arm.com>
Cc: Lorenzo Pieralisi <Lorenzo.Pieralisi@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Leif Lindholm <leif.lindholm@arm.com>
Cc: Ryan Harkin <ryan.harkin@linaro.org>
Fixes: 5078f77e "ARM64: juno: add NOR flash to device tree"
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NOlof Johansson <olof@lixom.net>

updates the bindings documents and dtsi file according to the review
comments[https://lkml.org/lkml/2015/9/21/670] from Rob Herring <robh@kernel.org>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: Nyankejian <yankejian@huawei.com>
Signed-off-by: Nhuangdaode <huangdaode@hisilicon.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

Enable building all dtb files when CONFIG_OF_ALL_DTBS is enabled. The dtbs
are not really dependent on a platform being enabled or any other kernel
config, so for testing coverage it is convenient to build all of the dtbs.
This builds all dts files in the tree, not just targets listed. This
is simpler for arm64 which has a bunch of sub-dirs.
Signed-off-by: NRob Herring <robh@kernel.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: linux-arm-kernel@lists.infradead.org

Juno R1 board sports a functional PCIe host bridge that is
compliant with the SBSA standard found [1] here. With the right
firmware that initialises the XpressRICH3 controller one can
use the generic Host Bridge driver to use the PCIe hardware.
Signed-off-by: NLiviu Dudau <Liviu.Dudau@arm.com>
Acked-by: NMark Rutland <mark.rutland@arm.com>

[1] http://infocenter.arm.com/help/topic/com.arm.doc.den0029a/

This patch adds build support for LS2080a QDS & RDB board DTS files
in the arm64 DTS Makefile.
Signed-off-by: NBhupesh Sharma <bhupesh.sharma@freescale.com>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

This patch adds the LS2080a DTS files for QDS and RDB boards
which support the LS2080a SoC.
Signed-off-by: NBhupesh Sharma <bhupesh.sharma@freescale.com>
Signed-off-by: NScott Wood <scottwood@freescale.com>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

This patch updates the LS2080a simulator DTS to add support of various
peripherals which are supported on the simulator platform and explicitly
disables those which are yet not supported on the platform.
Signed-off-by: NBhupesh Sharma <bhupesh.sharma@freescale.com>
Signed-off-by: NScott Wood <scottwood@freescale.com>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

Checkpatch complains about the text suggesting writing to
Free Software Foundation for GPLv2 license copy.

This patch removes the same from the .dtsi and .dts
Signed-off-by: NBhupesh Sharma <bhupesh.sharma@freescale.com>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

This patch updates the LS2080a DTSI (DTS Include) file to add
support for the following peripherals:
	- USB 3.0 Host
	- PMU
	- CCN-504
	- SATA
	- SPI
	- PCIe
Signed-off-by: NBhupesh Sharma <bhupesh.sharma@freescale.com>
Signed-off-by: NJaiprakash Singh <b44839@freescale.com>
Signed-off-by: NAlison Wang <alison.wang@freescale.com>
Signed-off-by: NLiu Gang <Gang.Liu@freescale.com>
Signed-off-by: NMinghuan Lian <Minghuan.Lian@freescale.com>
Signed-off-by: NShaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: NYangbo Lu <yangbo.lu@freescale.com>
Signed-off-by: NScott Wood <scottwood@freescale.com>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

Freescale is renaming the LS2085A SoC to LS2080A. This patch
addresses the same.
Signed-off-by: NBhupesh Sharma <bhupesh.sharma@freescale.com>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

Freescale will be a spinning-out a set of ARMv8 based SoCs which
will be based on a similar overall SoC architecture. So, this patch
converts the existing infrastructure in the arm64/dts, arm64/Kconfig
and arm64/configs to use the generic convention ARCH_LAYERSCAPE
in place of the more specific FSL_LS2085A, to save code duplication
later-on.
Signed-off-by: NBhupesh Sharma <bhupesh.sharma@freescale.com>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

The keyboard driver for GPIO buttons(gpio-keys) checks for one of the
two boolean properties to enable gpio buttons as wakeup source:
1. "wakeup-source" or
2. the legacy "gpio-key,wakeup"

However juno, ste-snowball and emev2-kzm9d dts file have a undetected
"wakeup" property to indictate the wakeup source.

This patch fixes it by making use of "wakeup-source" property.

Cc: Magnus Damm <magnus.damm@gmail.com>
Acked-by: NSimon Horman <horms@verge.net.au>
Reviewed-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NSudeep Holla <sudeep.holla@arm.com>
Signed-off-by: NOlof Johansson <olof@lixom.net>

The Juno motherboard has a NOR flash on the motherboard, enable
this to be accessed with the CFI flash driver. Results after
enabling MTD, MTD_CFI, MTD_PHYSMAP, MTD_PHYSMAP_OF,
MTD_CFI_INTELEXT:

8000000.flash: Found 2 x16 devices at 0x0 in 32-bit bank.
Manufacturer ID 0x000089 Chip ID 0x008919
Intel/Sharp Extended Query Table at 0x010A
Intel/Sharp Extended Query Table at 0x010A
Intel/Sharp Extended Query Table at 0x010A
Intel/Sharp Extended Query Table at 0x010A
Intel/Sharp Extended Query Table at 0x010A
Using buffer write method
Using auto-unlock on power-up/resume
cfi_cmdset_0001: Erase suspend on write enabled
erase region 0: offset=0x0,size=0x40000,blocks=255
erase region 1: offset=0x3fc0000,size=0x10000,blocks=4

Cc: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
Acked-by: NLiviu Dudau <Liviu.Dudau@arm.com>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

Commit 9ccd6080 "arm64: dts: add device tree for ARM SMM-A53x2 on
LogicTile Express 20MG" added a new dts file to arch/arm64 which
included "../../../../arm/boot/dts/vexpress-v2m-rs1.dtsi", i.e. a
.dtsi supplied by arch/arm.

Unfortunately this causes some issues for the split device tree
repository[0], since things get moved around there. In that context
the new .dts ends up at src/arm64/arm/vexpress-v2f-1xv7-ca53x2.dts
while the include is at src/arm/vexpress-v2m-rs1.dtsi.

The sharing of the .dtsi is legitimate since the baseboard is the same
for various vexpress systems whatever processor they use.

Previously I attempted to resolve this by creating a shared location
for such things but we have been unable to come to a consensus on
where that should be.

Instead this patch simply replaces the use of ../../ in the dts
/include/ with a symlink in arch/arm64/boot/dts/arm pointing to the
file arch/arm/boot/dts.

Since the split device tree repo will shortly be required to flatten
symlinks for other reasons this will cause the dtsi file to appear in
both src/arm and src/arm64 in the split repo, which is an improvement
on not building for arm64 now.

[0] https://git.kernel.org/cgit/linux/kernel/git/devicetree/devicetree-rebasing.git/Signed-off-by: NIan Campbell <ian.campbell@citrix.com>
Acked-by: NMark Rutland <mark.rutland@arm.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Kumar Gala <galak@codeaurora.org>
Cc: Liviu Dudau <liviu.dudau@arm.com>
Cc: Sudeep Holla <sudeep.holla@arm.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Kristina Martsenko <kristina.martsenko@arm.com>
Cc: Kevin Hilman <khilman@linaro.org>
Cc: Frank Rowand <frank.rowand@sonymobile.com>
Cc: Olof Johansson <olof@lixom.net>
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: arm@kernel.org
Cc: linux-kbuild@vger.kernel.org
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

Add clocks needed by Mediatek VENC and VENC_LT power domianis.
These clocks were needed by accessing subsystem's registers,
so they need to be enabled before power on these subsystems.
Signed-off-by: NJames Liao <jamesjj.liao@mediatek.com>
Signed-off-by: NMatthias Brugger <matthias.bgg@gmail.com>

This patch adds device nodes providing subsystem clocks on MT8173,
includes mmsys, imgsys, vdecsys, vencsys and vencltsys.
Signed-off-by: NJames Liao <jamesjj.liao@mediatek.com>
Reviewed-by: NDaniel Kurtz <djkurtz@chromium.org>
Acked-by: NSascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: NMatthias Brugger <matthias.bgg@gmail.com>

This patch enables spi buses on low speed and high speed expansion
connectors on DB410C
Signed-off-by: NSrinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: NAndy Gross <agross@codeaurora.org>

This patch enables i2c buses on low speed and high speed expansion
connectors on DB410C.
Signed-off-by: NSrinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: NAndy Gross <agross@codeaurora.org>

This patch adds missing support for i2c0 and i2c6, this support is
required to connect the i2c slaves on LS expansion on DB410c.
Signed-off-by: NSrinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: NAndy Gross <agross@codeaurora.org>

This patch fixes the i2c pinctrl sleep state by changing the pinconf
function to be in gpio mode rather than i2c.
Signed-off-by: NSrinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: NAndy Gross <agross@codeaurora.org>

Enable the eMMC on the APQ8016 SBC board (also known as DragonBoard 410c),
so that we can use its internal storage.
Signed-off-by: NGeorgi Djakov <georgi.djakov@linaro.org>
Signed-off-by: NAndy Gross <agross@codeaurora.org>

This patch adds the nodes required to support the UART1 node on the
MSM8916 and also fixes the sleep pins function for UART2.
Signed-off-by: NAndy Gross <agross@codeaurora.org>

Adds rng device tree node for msm8916 SoCs.
Signed-off-by: NStanimir Varbanov <stanimir.varbanov@linaro.org>
Signed-off-by: NAndy Gross <agross@codeaurora.org>

clock controller nodes which also support power domains (gdscs') need
to have a #power-domain-cells property. Add these for gcc and mmcc
nodes of msm8974, gcc of apq8084 and msm8916.
Also update gcc and mmcc bindings for it.
Signed-off-by: NRajendra Nayak <rnayak@codeaurora.org>
Acked-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NAndy Gross <agross@codeaurora.org>

The SCP firmware on Juno provides access to SoC sensors via the
SCPI. Add the sensor nodes to the device tree to enable this support.
Signed-off-by: NPunit Agrawal <punit.agrawal@arm.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Acked-by: NSudeep Holla <sudeep.holla@arm.com>
Acked-by: NLiviu Dudau <liviu.dudau@arm.com>

This patch adds the CPU clocks so that the CPU DVFS can be enabled.
Signed-off-by: NSudeep Holla <sudeep.holla@arm.com>
Acked-by: NLiviu Dudau <Liviu.Dudau@arm.com>
Cc: Jon Medhurst (Tixy) <tixy@linaro.org>

This patch adds CPU topology on Juno. It will be useful for ther other
IP blocks depending on this topology.
Signed-off-by: NSudeep Holla <sudeep.holla@arm.com>
Acked-by: NLiviu Dudau <Liviu.Dudau@arm.com>
Cc: Jon Medhurst (Tixy) <tixy@linaro.org>

This patch adds support for the MHU mailbox peripheral used on Juno by
application processors to communicate with remote SCP handling most of
the CPU/system power management. It also adds the SRAM reserving the
shared memory and SCPI message protocol using that shared memory.
Signed-off-by: NSudeep Holla <sudeep.holla@arm.com>
Acked-by: NLiviu Dudau <Liviu.Dudau@arm.com>
Cc: Jon Medhurst (Tixy) <tixy@linaro.org>

This adds BUS1 instance pinctrl for exynos7 soc.
Signed-off-by: NAlim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: NKukjin Kim <kgene@kernel.org>

The A57 and A53 PMUs in Juno support different events, so describe them
separately in both the Juno and Juno R1 DTs.
Signed-off-by: NMark Rutland <mark.rutland@arm.com>
Cc: Liviu Dudau <liviu.dudau@arm.com>
Acked-by: NWill Deacon <will.deacon@arm.com>
Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>

This patch adds all UART nodes for the Hi6220 SoC. Recently a board[1] has
been developed to standardize UART access across all the 96boards consumer
edition boards. To use this hardware on HiKey we must configure and enable
UART3. However, to ensure backward compatibility we must keep UART0 enabled
as well.

I have removed the hard coded clock index values in favor of using the ones
already defined in include/dt-bindings/clock/hi6220-clock.h.

Since UART0 needs to be soldered, it has been suggested to use the UART3 as
the default console.

This patch was boot tested on top of next-20150930, with both UART
configurations.

[1] http://www.seeedstudio.com/depot/96Boards-UART-p-2525.html?ref=newInBazaarSigned-off-by: NTyler Baker <tyler.baker@linaro.org>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

Add the base DTS for Altera's SoCFPGA Stratix 10 platform.
Signed-off-by: NDinh Nguyen <dinguyen@opensource.altera.com>
---
v4: Add a non-zero ranges property for /soc node
v3: change #address-cells and #size-cells to <2>
    change the GIC address to 0xfffc1000
    update the GIC virtual CPU reg length to 0x2000
v2: use interrupt-affinity for pmu node

This patch adds MT8173 spi bus controllers into device tree.
Signed-off-by: NLeilk Liu <leilk.liu@mediatek.com>
Reviewed-and-Tested-by: NNicolas Boichat <drinkcat@chromium.org>
Signed-off-by: NMatthias Brugger <matthias.bgg@gmail.com>

Node name in device tree should describe general class of the
device. Correct incorrect i2c node names.
Signed-off-by: NYingjoe Chen <yingjoe.chen@mediatek.com>
Reviewed-by: NDaniel Kurtz <djkurtz@chromium.org>
Signed-off-by: NMatthias Brugger <matthias.bgg@gmail.com>

Add L3/SoC DT subnodes to the APM X-Gene SoC EDAC node.
Signed-off-by: NLoc Ho <lho@apm.com>
Acked-by: NArnd Bergmann <arnd@arndb.de>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: "David S. Miller" <davem@davemloft.net>
Cc: devicetree@vger.kernel.org
Cc: Duc Dang <dhdang@apm.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Iyappan Subramanian <isubramanian@apm.com>
Cc: jcm@redhat.com
Cc: Keyur Chudgar <kchudgar@apm.com>
Cc: Kumar Gala <galak@codeaurora.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-edac <linux-edac@vger.kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: mchehab@osg.samsung.com
Cc: patches@apm.com
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Rameshwar Prasad Sahu <rsahu@apm.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Tanmay Inamdar <tinamdar@apm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Y Vo <yvo@apm.com>
Link: http://lkml.kernel.org/r/1443055261-8613-5-git-send-email-lho@apm.comSigned-off-by: NBorislav Petkov <bp@suse.de>

The idle-states bindings mandate that the entry-method string
in the idle-states node must be "psci" for ARM v8 64-bit systems,
but the examples in the bindings report a wrong entry-method string.
Owing to this typo, some dts in the kernel wrongly defined the
entry-method property, since they likely cut and pasted the example
definition without paying attention to the bindings definitions.

This patch fixes the typo in the DT idle states bindings examples and
respective dts in the kernel so that the bindings and related dts
files are made compliant.
Signed-off-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Howard Chen <howard.chen@linaro.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: NRob Herring <robh@kernel.org>

Add initial dtsi file to support Hisilicon Hip05-D02 Board with
support of CPUs in four clusters and each cluster has quard Cortex-A57.

Also add dts file to support Hip05-D02 development board.
Signed-off-by: NDing Tianhong <dingtianhong@huawei.com>
Signed-off-by: NKefeng Wang <wangkefeng.wang@huawei.com>
Signed-off-by: NWei Xu <xuwei5@hisilicon.com>

The Hisilicon Network Subsystem is a long term evolution IP which is
supposed to be used in Hisilicon ICT SoC. The IP, which is called hns
for short, is a TCP/IP acceleration engine, which can directly decode
TCP/IP stream and distribute them to different ring buffers.

HNS can be configured to work on different mode for different scenario.
This patch make use only some of the mode to make it as standard
ethernet NIC. The other mode will be added soon.

The whole function has 4 kernel sub-modules:

hnae: the HNS acceleration engine framework. It provides a abstract
interface between the engine and the upper layers which make use of the
engine by ring buffer.

hns_enet_drv: a standard ethernet driver that base on the ring buffer.

hns_dsaf: one of the implementation of HNS acceleration engine, which is
applied on Hililicon hip05, Hi1610 and other later-on SoCs

hns_mdio: the mdio control to the PHY, used by acceleration engine

This submit add basic config and documents
Signed-off-by: Nhuangdaode <huangdaode@hisilicon.com>
Signed-off-by: NKenneth Lee <liguozhu@huawei.com>
Signed-off-by: NYisen Zhuang <Yisen.Zhuang@huawei.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>