1. 20 12月, 2016 2 次提交
    • V
      ARC: mm: arc700: Don't assume 2 colours for aliasing VIPT dcache · 08fe0079
      Vineet Gupta 提交于
      An ARC700 customer reported linux boot crashes when upgrading to bigger
      L1 dcache (64K from 32K). Turns out they had an aliasing VIPT config and
      current code only assumed 2 colours, while theirs had 4. So default to 4
      colours and complain if there are fewer. Ideally this needs to be a
      Kconfig option, but heck that's too much of hassle for a single user.
      
      Cc: stable@vger.kernel.org
      Signed-off-by: NVineet Gupta <vgupta@synopsys.com>
      08fe0079
    • V
      ARC: mm: No need to save cache version in @cpuinfo · f64915be
      Vineet Gupta 提交于
      Historical MMU revisions have been paired with Cache revision updates
      which are captured in MMU and Cache Build Configuration Registers respectively.
      
      This was used in boot code to check for configurations mismatches,
      speically in simulations (such as running with non existent caches,
      non pairing MMU and Cache version etc). This can instead be inferred
      from other cache params such as line size. So remove @ver from post
      processed @cpuinfo which could be used later to save soem other
      interesting info.
      Signed-off-by: NVineet Gupta <vgupta@synopsys.com>
      f64915be
  2. 19 12月, 2016 1 次提交
  3. 15 12月, 2016 2 次提交
    • V
      ARCv2: intc: default all interrupts to priority 1 · 107177b1
      Vineet Gupta 提交于
      ARC HS Cores support configurable multiple interrupt priorities of upto
      16 levels. In commit dec2b284 ("ARCv2: intc: Allow interruption by
      lowest priority interrupt") we switched to 15 which seems a bit
      excessive given that there would be rare hardware implementing so many
      preemption levels AND running Linux. It would seem that 2 levels will be
      more common so switch to 1 as the default priority level. This will be
      the "lower" priority level saving 0 for implementing NMI style support.
      
      This scheme also works in systems with more than 2 prioity levels as
      well.
      Signed-off-by: NVineet Gupta <vgupta@synopsys.com>
      107177b1
    • V
      ARCv2: entry: document intr disable in hard isr · 78833e79
      Vineet Gupta 提交于
      And while at it - use the proper assembler macro which includes the
      optional irq tracing already - de-uglify'ing the code a bit
      Signed-off-by: NVineet Gupta <vgupta@synopsys.com>
      78833e79
  4. 14 12月, 2016 1 次提交
  5. 01 12月, 2016 14 次提交
  6. 30 11月, 2016 1 次提交
  7. 29 11月, 2016 2 次提交
  8. 28 11月, 2016 3 次提交
  9. 27 11月, 2016 8 次提交
  10. 26 11月, 2016 6 次提交